CH80566EE025DW S LGPN Intel, CH80566EE025DW S LGPN Datasheet - Page 16

• Manufacturer Part Number: CH80566EE025DW S LGPN
• Description: MPU, ATOM PROCESSOR, Z530P, U-FCBGA8
• Manufacturer: Intel
• Series: ATOM - Z5xxr

Specifications of CH80566EE025DW S LGPN

• Core Size: 32bit
• Program Memory Size: 512KB
• Cpu Speed: 533MHz
• Digital Ic Case Style: FCBGA
• No. Of Pins: 437
• Supply Voltage Range: 0.8V To 1.1V
• Operating Temperature Range: 0°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.1.1.1.2
2.1.1.2
2.1.1.2.1
16
C1/MWAIT Powerdown State
C1/MWAIT is a low-power state entered when one thread executes the MWAIT(C1)
instruction while the other thread is in the TC1 or greater thread state. Processor
behavior in the MWAIT state is identical to the AutoHALT state except that Monitor
events can cause the processor to return to the C0 state. See the Intel® 64 and IA-32
Architectures Software Developer's Manuals, Volume 2A: Instruction Set Reference, A-
M and Volume 2B: Instruction Set Reference, N-Z, for more information.
C2 State
Individual threads of the dual-threaded processor can enter the TC2 state by initiating
a P_LVL2 I/O read to the P_BLK or an MWAIT(C2) instruction. Once both threads have
C2 as a common state, the processor will transition to the C2 state—however, the
processor will not issue a Stop-Grant Acknowledge special bus cycle unless the
STPCLK# pin is also asserted by the chipset.
While in the C2 state, the processor will process bus snoops. The processor will enter
a snoopable sub-state described the following section (and shown in Figure 1), to
process the snoop and then return to the C2 state.
Stop-Grant State
When the STPCLK# pin is asserted, each thread of the processors enters the Stop-
Grant state within 1384 bus clocks after the response phase of the processor-issued
Stop-Grant Acknowledge special bus cycle. When the STPCLK# pin is de-asserted, the
core returns to its previous low-power state.
Since the AGTL+ signal pins receive power from the FSB, these pins should not be
driven (allowing the level to return to V
termination resistors in this state. In addition, all other input pins on the FSB should
be driven to the inactive state.
RESET# causes the processor to immediately initialize itself, but the processor will
stay in Stop-Grant state. When RESET# is asserted by the system, the STPCLK#,
SLP#, DPSLP#, and DPRSTP# pins must be de-asserted prior to RESET# de-assertion.
When re-entering the Stop-Grant state from the Sleep state, STPCLK# should be de-
asserted after the de-assertion of SLP#.
While in Stop-Grant state, the processor will service snoops and latch interrupts
delivered on the FSB. The processor will latch SMI#, INIT#, and LINT[1:0] interrupts
and will service only one of each upon return to the Normal state.
The PBE# signal may be driven when the processor is in Stop-Grant state. The PBE#
signal will be asserted if there is any pending interrupt or Monitor event latched within
the processor. Pending interrupts that are blocked by the EFLAGS.IF bit being clear
will still cause assertion of PBE#. Assertion of PBE# indicates to system logic that the
entire processor should return to the Normal state.
A transition to the Stop-Grant Snoop state occurs when the processor detects a snoop
on the FSB (see Section 2.1.1.2.2). A transition to the Sleep state (see
Section 2.1.1.3.1) occurs with the assertion of the SLP# signal.
CCP
) for minimum power drawn by the
Low Power Features
Datasheet