CH80566EE025DW S LGPN Intel, CH80566EE025DW S LGPN Datasheet - Page 62

• Manufacturer Part Number: CH80566EE025DW S LGPN
• Description: MPU, ATOM PROCESSOR, Z530P, U-FCBGA8
• Manufacturer: Intel
• Series: ATOM - Z5xxr

Specifications of CH80566EE025DW S LGPN

• Core Size: 32bit
• Program Memory Size: 512KB
• Cpu Speed: 533MHz
• Digital Ic Case Style: FCBGA
• No. Of Pins: 437
• Supply Voltage Range: 0.8V To 1.1V
• Operating Temperature Range: 0°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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STPCLK#
TCK
TDI
TDO
TEST[1:4]
THRMTRIP#
THRMDA
THRMDC
TMS
TRDY#
TRST#
VCCA
VCC
VSS
VSS/NCTF
Signal Name
Type
PWR
PWR
PWR
PWR
GND
GND
O
O
I
I
I
I
I
I
STPCLK# (Stop Clock), when asserted, causes the processor to
enter a low power Stop-Grant state. The processor issues a Stop-
Grant Acknowledge transaction, and stops providing internal
clock signals to all processor core units except the FSB and APIC
units. The processor continues to snoop bus transactions and
service interrupts while in Stop-Grant state. When STPCLK# is
de-asserted, the processor restarts its internal clock to all units
and resumes execution. The assertion of STPCLK# has no effect
on the bus clock—STPCLK# is an asynchronous input.
TCK (Test Clock) provides the clock input for the processor Test
Bus (also known as the Test Access Port).
TDI (Test Data In) transfers serial test data into the processor.
TDI provides the serial input needed for JTAG specification
support.
TDO (Test Data Out) transfers serial test data out of the
processor. TDO provides the serial output needed for JTAG
specification support.
Test Signals. All TEST signals can be left as No Connects.
The processor protects itself from catastrophic overheating by
use of an internal thermal sensor. This sensor is set well above
the normal operating temperature to ensure that there are no
false trips. The processor will stop all execution when the
junction temperature exceeds approximately 120°C. This
condition is signaled to the system by the THERMTRIP# (Thermal
Trip) pin.
Thermal Diode — Anode
Thermal Diode — Cathode
TMS (Test Mode Select) is a JTAG specification support signal
used by debug tools.
TRDY# (Target Ready) is asserted by the target to indicate that
it is ready to receive a write or implicit writeback data transfer.
TRDY# must connect the appropriate pins of both FSB agents.
TRST# (Test Reset) resets the Test Access Port (TAP) logic.
TRST# must be driven low during power on Reset.
VCCA provides isolated power for the internal processor core
PLLs.
Processor core power supply
Processor core ground node.
Non Critical to Function
Description
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