CH80566EE025DW S LGPN Intel, CH80566EE025DW S LGPN Datasheet - Page 60

• Manufacturer Part Number: CH80566EE025DW S LGPN
• Description: MPU, ATOM PROCESSOR, Z530P, U-FCBGA8
• Manufacturer: Intel
• Series: ATOM - Z5xxr

Specifications of CH80566EE025DW S LGPN

• Core Size: 32bit
• Program Memory Size: 512KB
• Cpu Speed: 533MHz
• Digital Ic Case Style: FCBGA
• No. Of Pins: 437
• Supply Voltage Range: 0.8V To 1.1V
• Operating Temperature Range: 0°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

60
INIT#
LINT[1:0]
LOCK#
PRDY#
PREQ#
PROCHOT#
Signal Name
Type
I/O,
I/O
O
I
I
I
INIT# (Initialization), when asserted, resets integer registers
inside the processor without affecting its internal caches or
floating-point registers. The processor then begins execution at
the power-on Reset vector configured during power-on
configuration. The processor continues to handle snoop requests
during INIT# assertion. INIT# is an asynchronous signal.
However, to ensure recognition of this signal following an
Input/Output Write instruction, it must be valid along with the
TRDY# assertion of the corresponding Input/Output Write bus
transaction. INIT# must connect the appropriate pins of both
FSB agents.
If INIT# is sampled active on the active to inactive transition of
RESET#, the processor reverses its FSB data and address signals
internally to ease mother board layout for systems where the
chipset is on the other side of the mother board.
D[63:0] => D[0:63]
A[31:3] => A[3:31]
DINV[3:0]# is also reversed.
LINT[1:0] (Local APIC Interrupt) must connect the appropriate
pins of all APIC Bus agents. When the APIC is disabled, the LINT0
signal becomes INTR, a maskable interrupt request signal, and
LINT1 becomes NMI, a non-maskable interrupt. INTR and NMI
are backward compatible with the signals of those names on the
Pentium processor. Both signals are asynchronous.
Both of these signals must be software configured using BIOS
programming of the APIC register space to be used either as
NMI/INTR or LINT[1:0]. Because the APIC is enabled by default
after Reset, operation of these pins as LINT[1:0] is the default
configuration.
LOCK# indicates to the system that a transaction must occur
automatically. This signal must connect the appropriate pins of
both FSB agents. For a locked sequence of transactions, LOCK#
is asserted from the beginning of the first transaction to the end
of the last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership
of the FSB, it will wait until it observes LOCK# deasserted. This
enables symmetric agents to retain ownership of the FSB
throughout the bus locked operation and ensure the automatic
operation of the lock.
The Probe Ready Signal used by debug tools to request debug
operation of the processor.
Probe Request Signal used by debug tools to request debug
operation of the processor.
As an output, PROCHOT# (Processor Hot) will go active when the
processor temperature monitoring sensor detects that the
processor has reached its maximum safe operating temperature.
This indicates that the processor Thermal Control Circuit (TCC)
has been activated, if enabled. As an input, assertion of
PROCHOT# by the system will activate the TCC, if enabled. The
TCC will remain active until the system de-asserts PROCHOT#.
Description
Datasheet