CH80566EE025DW S LGPN Intel, CH80566EE025DW S LGPN Datasheet - Page 36

• Manufacturer Part Number: CH80566EE025DW S LGPN
• Description: MPU, ATOM PROCESSOR, Z530P, U-FCBGA8
• Manufacturer: Intel
• Series: ATOM - Z5xxr

Specifications of CH80566EE025DW S LGPN

• Core Size: 32bit
• Program Memory Size: 512KB
• Cpu Speed: 533MHz
• Digital Ic Case Style: FCBGA
• No. Of Pins: 437
• Supply Voltage Range: 0.8V To 1.1V
• Operating Temperature Range: 0°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I
I
I
36
CCA
CCP
CCP
Symbol
+ I
+ I
CCPC6
CCPC6
I
I
I
CC
CCP
CCP
NOTES:
for V
+ I
+ I
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. The V
11. Unless otherwise noted, all specifications in this table are based on estimates and
12. V
13. The V
14. V
CCPC6
CCPC6
CCA
Each processor is programmed with a maximum valid voltage identification value
(VID), which is set at manufacturing and cannot be altered. Individual maximum VID
values are calibrated during manufacturing such that two processors at the same
frequency may have different settings within the VID range. Note that this differs from
the VID employed by the processor during a power management event (Thermal
Monitor 2, Enhanced Intel SpeedStep technology, or Enhanced Halt State). Typical
AVID range is 0.75 V to 1.1 V.
The voltage specifications are assumed to be measured across VCC_SENSE and
VSS_SENSE pins at the socket with a 100-MHz bandwidth oscilloscope, 1.5-pF
maximum probe capacitance, and 1-MΩ minimum impedance. The maximum length of
ground wire on the probe should be less than 5 mm. Ensure external noise from the
system is not coupled in the scope probe.
Specified at 90°C T
Specified at the nominal V
Measured at the bulk capacitors on the motherboard.
V
Based on simulations and averaged over the duration of any change in current.
Specified by design/characterization at nominal V
This is a power-up peak current specification, which is applicable when V
V
This is a steady-state I
V
(burn in voltage is higher).
simulations or empirical data. These specifications will be updated with characterized
data from silicon measurements at a later date.
1.05 V -5/+10% on all power states.
1.05 V while exiting C6 (Deep Power Down Technology State) at least 5µs before
V
during V
Supply
CC,BOOT
CC_CORE
CC_CORE
CCP
CCP
CC_CORE
before V
after V
may be turned off during C6 power state— V
(voltage rail which is turned off in C6, with SPLIT VTT Enabled) should ramp to
CC
CC
Parameter
tolerance is shown in Figure 6 and Figure 7.
maximum supported by the process is 1.1 V but the parameter can change
power supply needs to be set to 0.3V during C6 power state.
CCP
is low.
are high.
ramps to LFM VID. In addition, V
CC
CC
Stable
ramp coming out of C6.
Stable
J
.
CC
current specification, which is applicable when both V
CC
.
Min.
—
—
—
CCPC6
rail should remain at 1.05 -5/+10%
Typ.
CC
CCPC6
—
—
—
. Not 100% tested.
must always be powered on to
Electrical Specifications
Max.
130
2.5
1.5
Unit
mA
CCP
A
A
is high and
Datasheet
CCP
Notes
and
8
9
11