CH80566EE025DW S LGPN Intel, CH80566EE025DW S LGPN Datasheet - Page 58

• Manufacturer Part Number: CH80566EE025DW S LGPN
• Description: MPU, ATOM PROCESSOR, Z530P, U-FCBGA8
• Manufacturer: Intel
• Series: ATOM - Z5xxr

Specifications of CH80566EE025DW S LGPN

• Core Size: 32bit
• Program Memory Size: 512KB
• Cpu Speed: 533MHz
• Digital Ic Case Style: FCBGA
• No. Of Pins: 437
• Supply Voltage Range: 0.8V To 1.1V
• Operating Temperature Range: 0°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

58
DBSY#
DEFER#
DINV[3:0]#
DPRSTP#
DPSLP#
DPWR#
DRDY#
DSTBN[3:0]#
DSTBP[3:0]#
Signal Name
Type
I/O
I/O
I/O
I/O
I
I
I
I
I
DBSY# (Data Bus Busy) is asserted by the agent responsible for
driving data on the FSB to indicate that the data bus is in use.
The data bus is released after DBSY# is de-asserted. This signal
must connect the appropriate pins on both FSB agents.
DEFER# is asserted by an agent to indicate that a transaction
cannot be guaranteed in-order completion. Assertion of DEFER#
is normally the responsibility of the addressed memory or
Input/Output agent. This signal must connect the appropriate
pins of both FSB agents.
DINV[3:0]# (Data Bus Inversion) are source synchronous and
indicates the polarity of the D[63:0]# signals. The DINV[3:0]#
signals are activated when the data on the data bus is inverted.
The bus agent will invert the data bus signals if more than half
the bits, within the covered group, would change level in the next
cycle. DINV[3:0]# assignment to data bus signals is shown
below.
Bus Signal
DINV[3]#
DINV[2]#
DINV[1]#
DINV[0]#
DPRSTP# when asserted on the platform causes the processor to
transition from the Deep Sleep State to the Deeper Sleep state.
In order to return to the Deep Sleep State, DPRSTP# must be
de-asserted. DPRSTP# is driven by the SCH chipset.
DPSLP# when asserted on the platform causes the processor to
transition from the Sleep State to the Deep Sleep state. In order
to return to the Sleep State, DPSLP# must be de-asserted.
DPSLP# is driven by the SCH chipset.
DPWR# is a control signal from the Intel® SCH used to reduce
power on the processor data bus input buffers.
DRDY# (Data Ready) is asserted by the data driver on each data
transfer, indicating valid data on the data bus. In a multi-
common clock data transfer, DRDY# may be de-asserted to
insert idle clocks. This signal must connect the appropriate pins
of both FSB agents.
Data strobe used to latch in D[63:0]#.
Signals
D[15:0]#
D[31:16]#
D[47:32]#
D[63:48]#
Data strobe used to latch in D[63:0]#.
Signals
D[15:0]#
D[31:16]#
D[47:32]#
D[63:48]#
Data Bus Signals
D[63:48]#
D[47:32]#
D[31:16]#
D[15:0]#
Associated Strobe
DINV[0]#, DSTBN[0]#
DINV[1]#, DSTBN[1]#
DINV[2]#, DSTBN[2]#
DINV[3]#, DSTBN[3]#
Associated Strobe
DINV[0]#, DSTBP[0]#
DINV[1]#, DSTBP[1]#
DINV[2]#, DSTBP[2]#
DINV[3]#, DSTBP[3]#
Description
Datasheet