CH80566EE025DW S LGPN Intel, CH80566EE025DW S LGPN Datasheet - Page 32

• Manufacturer Part Number: CH80566EE025DW S LGPN
• Description: MPU, ATOM PROCESSOR, Z530P, U-FCBGA8
• Manufacturer: Intel
• Series: ATOM - Z5xxr

Specifications of CH80566EE025DW S LGPN

• Core Size: 32bit
• Program Memory Size: 512KB
• Cpu Speed: 533MHz
• Digital Ic Case Style: FCBGA
• No. Of Pins: 437
• Supply Voltage Range: 0.8V To 1.1V
• Operating Temperature Range: 0°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Table 5. FSB Pin Groups
Implementation of a source synchronous data bus determines the need to specify two
sets of timing parameters. One set is for common clock signals which are dependent
upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, and so on.) and the second set
is for the source synchronous signals which are relative to their respective strobe lines
(data and address) as well as the rising edge of BCLK0. Asynchronous signals are still
present (A20M#, IGNNE#, and so on.) and can become active at any time during the
clock cycle. Table 5 identifies which signals are common clock, source synchronous,
and asynchronous.
NOTES:
AGTL+ Common
Clock Input
AGTL+ Common
Clock I/O
CMOS Source
Synchronous I/O
AGTL+ Strobes
CMOS Input
Open Drain Output
Open Drain I/O
CMOS Output
CMOS Input
Open Drain Output
FSB Clock
Power/Other
1.
2.
3.
4.
Signal Group
Refer to Chapter 4 for signal descriptions and termination requirements.
In processor systems where there is no debug port implemented on the system board,
these signals are used to support a debug port interposer. In systems with the debug
port implemented on the system board, these signals are no connects.
PROCHOT# signal type is open drain output and CMOS input.
On die termination differs from other AGTL+ signals.
Synchronous
to BCLK[1:0]
Synchronous
to BCLK[1:0]
Synchronous
to assoc.
strobe
Synchronous
to BCLK[1:0]
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Synchronous
to TCK
Synchronous
to TCK
Clock
Type
BPRI#, DEFER#, PREQ#4, RESET#, RS[2:0]#,
TRDY#, DPWR#
ADS#, BNR#, BPM[3:0]#, BR0#, DBSY#, DRDY#,
HIT#, HITM#, LOCK#, PRDY#
Signals
REQ[4:0]#, A[16:3]#
A[31:17]#
D[15:0]#
D[31:16]#
D[47:32]#
D[63:48]#
Strobes always use AGTL signaling—data pins are
CMOS only.
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
DPRSTP#, DPSLP#, IGNNE#, INIT#, LINT0/INTR,
LINT1/ NMI, PWRGOOD, SMI#, SLP#, STPCLK#
FERR#, THERMTRIP#, IERR#
PROCHOT#3
VID[6:0], BSEL[2:0]
TCK, TDI, TMS, TRST#
BCLK[1:0]
COMP[3:0], HFPLL, CMREF, GTLREF, /DCLK, /ADK,
THERMDA, THERMDC, VCC, VCCA, VCCP,
VCC_SENSE, VSS, VSS_SENSE, VCCFUSE, VCCPC6
TDO
Signals1
Associated Strobe
ADSTB0#
ADSTB1#
DSTBP0#, DSTBN0#
DSTBP1#, DSTBN1#
DSTBP2#, DSTBN2#
DSTBP3#, DSTBN3#
Electrical Specifications
Datasheet