CH80566EE025DW S LGPN Intel, CH80566EE025DW S LGPN Datasheet - Page 25

• Manufacturer Part Number: CH80566EE025DW S LGPN
• Description: MPU, ATOM PROCESSOR, Z530P, U-FCBGA8
• Manufacturer: Intel
• Series: ATOM - Z5xxr

Specifications of CH80566EE025DW S LGPN

• Core Size: 32bit
• Program Memory Size: 512KB
• Cpu Speed: 533MHz
• Digital Ic Case Style: FCBGA
• No. Of Pins: 437
• Supply Voltage Range: 0.8V To 1.1V
• Operating Temperature Range: 0°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Low Power Features
2.5
2.5.1
Datasheet
FSB Low Power Enhancements
The processor incorporates FSB low power enhancements:
The processor incorporates the DPWR# signal that controls the data bus input buffers
on the processor. The DPWR# signal disables the buffers when not used and activates
them only when data bus activity occurs, resulting in significant power savings with no
performance impact. BPRI# control also allows the processor address and control
input buffers to be turned off when the BPRI# signal is inactive. Dynamic Bus Parking
allows a reciprocal power reduction in chipset address and control input buffers when
the processor de-asserts its BR0# pin. The On-Die Termination on the processor FSB
buffers is disabled when the signals are driven low, resulting in additional power
savings. The low I/O termination voltage is on a dedicated voltage plane independent
of the core voltage, enabling low I/O switching power at all times.
CMOS Front Side Bus
The processor has a hybrid signaling mode—where data and address busses run in
CMOS mode and strobe signals operate in GTL mode. The reason to use GTL on strobe
signals is to improve signal integrity. The implementation of a CMOS bus offers
substantial power savings when compared with the traditional AGTL+ bus.
• BPRI# control for address and control input buffers
• Dynamic Bus Parking
• Dynamic On Die Termination disabling
• Low V
• CMOS Front Side Bus
CCP
(I/O termination voltage)
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