PIC16F785-E/SS Microchip Technology, PIC16F785-E/SS Datasheet - Page 107

• Manufacturer Part Number: PIC16F785-E/SS
• Description: 20 PIN, 3.5 KB STD FLASH, 128 RAM, 18 I/O PB FREE,
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F785-E/SS

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT20SS1-1 - SOCKET TRANSITION 20DIP 20SSOPAC162060 - HEADER INTRFC MPLAB ICD2 20PIN
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.2
To read a data memory location, the user must write the
address to the EEADR register and then set control bit
RD of the EECON1 Register, as shown in Example 14-
1. The data is available, in the very next cycle, in the
EEDAT register. Therefore, it can be read in the next
instruction. EEDAT holds this value until another read,
or until it is written to by the user (during a write
operation).
EXAMPLE 14-1:
14.3
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data
to the EEDAT register. Then the user must follow a
specific sequence to initiate the write for each byte, as
shown in Example 14-2.
EXAMPLE 14-2:
The write will not initiate if the sequence in Example 14-2
is not followed exactly (write 55h to EECON2, write AAh
to EECON2, then set WR bit) for each byte. It is strongly
recommended that interrupts be disabled during this
code segment. A cycle count is executed during the
required sequence. Any number that is not equal to the
required cycles to execute the required sequence will
prevent the data from being written into the EEPROM.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating the EEPROM. The WREN bit is not cleared by
hardware.
© 2008 Microchip Technology Inc.
BSF
BCF
MOVLW
MOVWF
BSF
MOVF
BSF
BCF
BSF
BCF
BTFSC
GOTO
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
Reading the EEPROM Data
Memory
Writing to the EEPROM Data
Memory
STATUS,RP0
STATUS,RP1
CONFIG_ADDR
EEADR
EECON1,RD
EEDAT,W
STATUS,RP0
STATUS,RP1
EECON1,WREN ;Enable write
INTCON,GIE
INTCON,GIE
$-2
55h
EECON2
AAh
EECON2
EECON1,WR
INTCON,GIE
DATA EEPROM READ
DATA EEPROM WRITE
;Bank 1
;
;
;Address to read
;EE Read
;Move data to W
;Bank 1
;
;Disable INTs
;See AN-576
;
;Unlock write
;
;
;
;Start the write
;Enable INTs
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is
cleared in the hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. The EEIF bit of the
PIR1 Register must be cleared by software.
14.4
Depending on the application, good programming
practice may dictate that the value written to the data
EEPROM should be verified (see Example 14-3) to the
desired value to be written.
EXAMPLE 14-3:
14.4.1
The data EEPROM is a high-endurance, byte address-
able array that has been optimized for the storage of
frequently
variables or other data that are updated often). When
variables in one section change frequently, while vari-
ables in another section do not change, it is possible to
exceed the total number of write cycles to the
EEPROM (specification D124) without exceeding the
total number of write cycles to a single byte (specifica-
tions D120 and D120A). If this is the case, then a
refresh of the array must be performed. For this reason,
variables that change infrequently (such as constants,
IDs, calibration, etc.) should be stored in Flash program
memory.
14.5
There are conditions when the user may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built in. On power-up, WREN is cleared. Also, the
Power-up
EEPROM write.
The write initiate sequence and the WREN bit helps
prevent an accidental write during a brown-out, power
glitch and software malfunction.
BSF
BCF
MOVF
BSF
XORWF
BTFSS
GOTO
PIC16F785/HV785
Write Verify
Protect Against Spurious Write
USING THE DATA EEPROM
changing
Timer
STATUS,RP0
STATUS,RP1
EEDAT,W
EECON1,RD
EEDAT,W
STATUS,Z
WRITE_ERR
WRITE VERIFY
(64 ms
information
;Bank 1
;
;EEDAT not changed
;YES, Read the
; value written
;
;Is data the same
;No, handle error
;Yes, continue
from previous write
duration)
DS41249E-page 105
(e.g.,
prevents
program