PIC16F785-E/SS Microchip Technology, PIC16F785-E/SS Datasheet - Page 95

• Manufacturer Part Number: PIC16F785-E/SS
• Description: 20 PIN, 3.5 KB STD FLASH, 128 RAM, 18 I/O PB FREE,
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F785-E/SS

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT20SS1-1 - SOCKET TRANSITION 20DIP 20SSOPAC162060 - HEADER INTRFC MPLAB ICD2 20PIN
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REGISTER 13-1:
© 2008 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3-2
bit 1
bit 0
Note 1: Blanking is disabled when operating in complementary mode. See COMOD<1:0> bits in the PWMCON1
PRSEN
R/W-0
register (Register 13-5) for more information.
PRSEN: PWM Restart Enable bit
1 = Upon auto-shutdown, the PWMASE shutdown bit clears automatically once the shutdown condi-
0 = Upon auto-shutdown, the PWMASE must be cleared in firmware to restart the PWM.
PASEN: PWM Auto-Shutdown Enable bit
0 = PWM auto-shutdown is disabled
1 = V
BLANK2: PH2 Blanking bit
1 = The PH2 pin is active for a minimum of 1/2 of an F
0 = The PH2 pin is reset as soon as the comparator trigger is active
BLANK1: PH1 Blanking bit
1 = The PH1 pin is active for a minimum of 1/2 of an F
0 = The PH1 pin is reset as soon as the comparator trigger is active
SYNC<1:0>: SYNC Pin Function bits
0X = SYNC pin not used for PWM. PWM acts as its own master. RB7/SYNC pin is available for gen-
10 = SYNC pin acts as system slave, receiving the PWM counter reset pulse
11 = SYNC pin acts as system master, driving the PWM counter reset pulse
PH2EN: PH2 Pin Enabled bit
1 = The PH2 pin is driven by the PWM signal
0 = The PH2 pin is not used for PWM functions
PH1EN: PH1 Pin Enabled bit
1 = The PH1 pin is driven by the PWM signal
0 = The PH1 pin is not used for PWM functions
PASEN
R/W-0
tion goes away. The PWM restarts automatically.
IL
PWMCON0: PWM CONTROL REGISTER 0
eral purpose I/O.
on INT pin will cause auto-shutdown event
W = Writable bit
‘1’ = Bit is set
BLANK2
R/W-0
(1)
(1)
BLANK1
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SYNC1
R/W-0
PIC16F785/HV785
OSC
OSC
clock period after it is set
clock period after it is set
SYNC0
R/W-0
x = Bit is unknown
PH2EN
R/W-0
DS41249E-page 93
PH1EN
R/W-0
bit 0