PIC16F785-E/SS Microchip Technology, PIC16F785-E/SS Datasheet - Page 51

• Manufacturer Part Number: PIC16F785-E/SS
• Description: 20 PIN, 3.5 KB STD FLASH, 128 RAM, 18 I/O PB FREE,
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F785-E/SS

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT20SS1-1 - SOCKET TRANSITION 20DIP 20SSOPAC162060 - HEADER INTRFC MPLAB ICD2 20PIN
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.0
The Timer0 module timer/counter has the following
features:
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
Figure 5-1 is a block diagram of the Timer0 module and
the prescaler shared with the WDT.
5.1
Timer mode is selected by clearing the T0CS bit of the
OPTION Register. In Timer mode, the Timer0 module
will increment every instruction cycle (without pres-
caler). If TMR0 is written, the increment is inhibited for
the following two instruction cycles. The user can work
around this by writing an adjusted value to the TMR0
register.
Counter mode is selected by setting the T0CS bit of the
OPTION Register. In this mode, the Timer0 module will
increment either on every rising or falling edge of pin
FIGURE 5-1:
© 2008 Microchip Technology Inc.
RA2/AN2/T0CKI/INT/C1OUT
Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION_REG (see Register 2.2.2.3).
SWDTEN
WDTE
(= F
CLKOUT
T0SE
OSC
31 kHz
INTRC
2: WDTPS<3:0> are bits in the WDTCON register (see Register 15-2).
TIMER0 MODULE
Timer0 Operation
/4)
(1)
Watchdog
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Timer
T0CS
0
1
(1)
PSA
Prescaler
0
1
16-bit
(1)
WDTPS<3:0>
16
Prescaler
8-bit
8
PS<0:2>
(2)
RA2/AN2/T0CKI/INT/C1OUT. The incrementing edge
is determined by the source edge (T0SE) control bit of
the OPTION Register. Clearing the T0SE bit selects the
rising edge.
5.2
A Timer0 interrupt is generated when the TMR0
register timer/counter overflows from FFh to 00h. This
overflow sets the T0IF bit of the INTCON Register. The
interrupt can be masked by clearing the T0IE bit of the
INTCON Register. The T0IF bit must be cleared in soft-
ware by the Timer0 module Interrupt Service Routine
before re-enabling this interrupt. The Timer0 interrupt
cannot wake the processor from Sleep since the timer
is shut-off during Sleep.
(1)
Note 1: Counter mode has specific external clock
PIC16F785/HV785
2: The ANSEL0 (91h) register must be ini-
Timer0 Interrupt
PSA
PSA
requirements.
tialized to configure an analog channel as
a digital input. Pins configured as analog
inputs will read ‘0’.
1
0
1
0
(1)
(1)
SYNC 2
Cycles
Time-out
WDT
Data Bus
Set Flag bit T0IF
DS41249E-page 49
8
TMR0
on Overflow