PIC16F785-E/SS Microchip Technology, PIC16F785-E/SS Datasheet - Page 125

• Manufacturer Part Number: PIC16F785-E/SS
• Description: 20 PIN, 3.5 KB STD FLASH, 128 RAM, 18 I/O PB FREE,
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F785-E/SS

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT20SS1-1 - SOCKET TRANSITION 20DIP 20SSOPAC162060 - HEADER INTRFC MPLAB ICD2 20PIN
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.6
The Power-down mode is entered by executing a
SLEEP instruction.
If the Watchdog Timer is enabled:
• WDT will be cleared but keeps running
• PD bit in the STATUS register is cleared
• TO bit is set
• Oscillator driver is turned off
• I/O ports maintain the status they had before
For lowest current consumption in this mode, all I/O
pins should be either at V
circuitry drawing current from the I/O pin and all unused
peripheral modules should be disabled. Digital I/O pins
that are high-impedance inputs should be pulled high,
or low, externally to avoid switching currents caused by
floating inputs. The T0CKI input should also be at V
or
contribution from on-chip pull-ups on PORTA should be
considered.
The MCLR pin must be at a logic high level.
15.6.1
The device can wake-up from Sleep through one of the
following events:
1.
2.
3.
The first event will cause a device Reset. The two latter
events are considered a continuation of program exe-
cution. The TO and PD bits in the STATUS register can
be used to determine the cause of device Reset. The
PD bit, which is set on power-up, is cleared when Sleep
is invoked. TO bit is cleared if WDT Wake-up occurred.
The following peripheral interrupts can wake the device
from Sleep:
• TMR1 interrupt; Timer1 must be operating as an
• CCP Capture mode interrupt
• A/D conversion (when A/D clock source is RC)
• EEPROM write operation completion
• Comparator output changes state
• Interrupt-on-change
• External Interrupt from INT pin
Other peripherals cannot generate interrupts since,
during Sleep, no on-chip clocks are present.
© 2008 Microchip Technology Inc.
SLEEP was executed (driving high, low or high-
impedance).
Note:
asynchronous counter.
V
External Reset input on MCLR pin
Watchdog Timer Wake-up (if WDT was enabled)
Interrupt from RA2/AN2/T0CKI/INT/C1OUT pin,
PORTA change or a peripheral interrupt.
SS
Power-Down Mode (Sleep)
for
It should be noted that a Reset generated
by a WDT time-out does not drive MCLR
pin low.
WAKE-UP FROM SLEEP
lowest
current
DD
or V
SS
consumption.
, with no external
The
DD
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit (and PEIE bit where applicable)
must be set (enabled). Wake-up is regardless of the
state of the GIE bit. If the GIE bit is clear (disabled), the
device continues execution of the instruction after the
SLEEP instruction. If the GIE bit is set (enabled), the
device executes the instruction after the SLEEP instruc-
tion, then branches to the interrupt address (0004h). In
cases where the execution of the instruction, following
SLEEP, is not desired, the user should place a NOP
after the SLEEP instruction.
The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.
15.6.2
When global interrupts are disabled (i.e., GIE bit of the
INTCON register is clear) and any interrupt source has
both its interrupt enable bit and interrupt flag bit set, one
of the following will occur:
• If the interrupt occurs before the execution of a
• If the interrupt occurs during or after the execu-
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
When global interrupts are disabled, a CLRWDT
instruction should be executed before a SLEEP
instruction to ensure that the WDT is cleared.
Note:
SLEEP instruction, the SLEEP instruction will
complete as a NOP. Therefore, the WDT and WDT
prescaler and postscaler (if enabled) will not be
cleared, the TO bit will not be set and the PD bit
will not be cleared.
tion of a SLEEP instruction, the device will
immediately wake-up from Sleep. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT prescaler
and postscaler (if enabled) will be cleared, the TO
bit will be set, and the PD bit will be cleared.
PIC16F785/HV785
If the global interrupts are disabled (GIE is
cleared), but any interrupt source has both
its interrupt enable bit and the correspond-
ing interrupt flag bits set (including PEIE,
where applicable), the device will immedi-
ately wake-up from Sleep. The SLEEP
instruction is completely executed.
WAKE-UP USING INTERRUPTS
DS41249E-page 123