PIC16F785-E/SS Microchip Technology, PIC16F785-E/SS Datasheet - Page 60

20 PIN, 3.5 KB STD FLASH, 128 RAM, 18 I/O PB FREE,

PIC16F785-E/SS

Manufacturer Part Number
PIC16F785-E/SS
Description
20 PIN, 3.5 KB STD FLASH, 128 RAM, 18 I/O PB FREE,
Manufacturer
Microchip Technology
Series
PIC® 16Fr

Specifications of PIC16F785-E/SS

Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 14x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT20SS1-1 - SOCKET TRANSITION 20DIP 20SSOPAC162060 - HEADER INTRFC MPLAB ICD2 20PIN
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
PIC16F785/HV785
8.1
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin RC5/CCP1. An event is defined as one of the
following and is configured by CCP1CON<3:0>:
• Every falling edge
• Every rising edge
• Every 4th rising edge
• Every 16th rising edge
When a capture is made, the interrupt request flag bit
CCP1IF of the PIR1 Register is set. The interrupt flag
must be cleared in software. If another capture occurs
before the value in register CCPR1 is read, the old cap-
tured value is overwritten by the new captured value.
8.1.1
In Capture mode, the RC5/CCP1 pin should be config-
ured as an input by setting the TRISC<5> bit.
FIGURE 8-1:
8.1.2
Timer1 must be running in Timer mode or Synchro-
nized Counter mode for the CCP module to use the
capture feature. In Asynchronous Counter mode, the
capture operation may not work.
8.1.3
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE of the PIE1 Register clear to avoid false inter-
rupts and should clear the flag bit CCP1IF of the PIR1
Register following any such change in Operating mode.
DS41249E-page 58
RC5/CCP1
pin
Note:
Capture Mode
Edge Detect
Q’s
CCP1 PIN CONFIGURATION
If the RC5/CCP1 pin is configured as an
output, a write to the port can cause a
capture condition.
Prescaler
÷ 1, 4, 16
TIMER1 MODE SELECTION
SOFTWARE INTERRUPT
and
CCP1CON<3:0>
Set Flag bit CCP1IF
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
(PIR1<5>)
Capture
Enable
CCPR1H
TMR1H
CCPR1L
TMR1L
8.1.4
There are four prescaler settings specified by bits
CCP1M<3:0> of the CCP1CON Register. Whenever
the CCP module is turned off, or the CCP module is not
in Capture mode, the prescaler counter is cleared. Any
Reset will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
a non-zero prescaler. Example 8-1 shows the recom-
mended method for switching between capture pres-
calers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
EXAMPLE 8-1:
8.2
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC5/CCP1 pin is:
• Driven high
• Driven low
• Remains unchanged
The action on the pin is based on the value of control
bits CCP1M<3:0> of the CCP1CON Register. At the
same time, interrupt flag bit CCP1IF of the PIR1 Regis-
ter is set.
FIGURE 8-2:
CLRF
MOVLW
MOVWF
RC5/CCP1
Pin
Special Event Trigger will:
• clear TMR1H and TMR1L registers
• NOT set interrupt flag bit TMR1F (PIR1<0>)
• set the GO/DONE bit (ADCON0<1>)
Output Enable
TRISC<5>
Compare Mode
CCP1CON
NEW_CAPT_PS ;Load the W reg with
CCP1CON
CCP PRESCALER
Q
Special Event Trigger
CCP1CON<3:0>
R
S
Mode Select
Output
CHANGING BETWEEN
CAPTURE PRESCALERS
COMPARE MODE
OPERATION BLOCK
DIAGRAM
Logic
;Turn CCP module off
; the new prescaler
; move value and CCP ON
;Load CCP1CON with this
; value
© 2008 Microchip Technology Inc.
Set Flag bit CCP1IF
4
(PIR1<5>)
Match
CCPR1H CCPR1L
TMR1H
Comparator
TMR1L

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