IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 24

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

2–14
Figure 2–1. System Naming
DDR and DDR2 SDRAM Controller Compiler User Guide
Other Logic
25. IP Toolbench uses a prefix (for example, ddr_, or ddr2_) for the names of all
26. If you want to access the manual timing settings, click the Manual Timing tab.
27. Choose Automatic, Always, or Never in the Reclock resynchronized data to the
28. Turn on Manual resynchronization control, only if you want to override the
29. Turn on Manual postamble control, only if you want to override the
30. Turn on your timing analysis options.
31. Click Finish.
PLL
memory interface pins. Enter a prefix for all memory interface pins associated
with this custom variation.
Otherwise, click Finish and proceed to
f
positive edge list.
wizard-calculated values.
1
f
wizard-calculated values.
1
f
Under most circumstances, IP Toolbench calculates the correct
resynchronization settings for your custom variation.
Under most circumstances, IP Toolbench calculates the correct postamble
settings for your custom variation.
For more information on the manual timing settings, refer to
Manual Timing
For more information on resynchronization, refer to
on page
For more information on postamble, refer to
page
Example Top-Level Design
A–10.
example_top
A–4.
DDR SDRAM Controller
auk_ddr_sdram
my_ddr_sdram
Settings.
my_system
Data Path
System
“Constraints” on page
DDR SDRAM
Interface
MegaWizard Plug-In Manager Design Flow
“DQS Postamble” on
© March 2009 Altera Corporation
DDR SDRAM
“Resynchronization”
2–15.
Chapter 2: Getting Started
Appendix A,