IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 33

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 2: Getting Started
MegaWizard Plug-In Manager Design Flow
© March 2009 Altera Corporation
f
1
1
4. Click Next.
5. Edit the PLL parameters in the ALTPLL MegaWizard Plug-In.
For more information on the ALTPLL megafunction, refer to the Quartus II Help or
click Documentation in the ALTPLL MegaWizard Plug-In.
Compile & Perform Timing Analysis
When you compile a project after generating or editing and re-generating your
variation, the auto_add_ddr_constraints.tcl script automatically calls the constraints
script specific to each instance of the controller in your design. Each constraints script
performs the following procedure:
■
■
■
If the script successfully adds the new constraints, it does not run when you next
compile.
To prevent the constraints script from running, turn off Automatically run add
constraints script in the wizard. To manually prevent the script from running, open a
Quartus II Tcl Console window and enter the following command:
set_global_assignment -name PRE_FLOW_SCRIPT_FILE -remove
The constraints script analyzes and elaborates your design, to automatically extract
the hierarchy to your variation. To prevent the constraints script analyzing and
elaborating your design, turn on Enable Hierarchy Control in the wizard, and enter
the correct hierarchy path to your datapath (refer to step
To compile your design, choose Start Compilation (Processing menu), which runs the
add constraints scripts, compiles the example design, and performs timing analysis.
If the compilation does not reach the frequency requirements, follow these steps:
1. Choose Settings (Assignments menu).
2. Click Analysis & Synthesis Settings in the Category list.
3. In Optimization Technique, select Speed.
4. Click Fitter Settings in the Category list.
5. In Fitter effort, select Standard Fit (highest effort).
6. Click OK.
7. Recompile the example design by clicking Start Compilation (Processing menu).
Checks if there is a remove_constraints.tcl script specific to this instance of the
controller, and if so, runs it to remove the previous set of constraints.
Analyses and elaborates the design to detect the exact hiearchy and then adds the
new set of constraints.
Creates a new, matching remove_constraints.tcl script, which you can use to
remove the constraints from your design, if necessary.
1
To achieve a higher frequency, turn on the Insert extra pipeline registers in
the datapath option (refer to step
5
on
DDR and DDR2 SDRAM Controller Compiler User Guide
page
2–12).
24
on
page
2–13).
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