IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 61

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 3: Functional Description
Interfaces & Signals
Figure 3–17. DDR SDRAM Device Initialization Timing
© March 2009 Altera Corporation
f
DDR Command
local_init_done
ddr_cas_n
ddr_ras_n
ddr_we_n
ddr_cs_n
Key:
P = PCH
L = LMR
A = ARF
ddr_cke
ddr_ba
ddr_a
DDR SDRAM Initialization Timing
DDR SDRAM and DDR2 SDRAM initialization timing is different. For DDR2 SDRAM
initialization timing, refer to
The DDR SDRAM controller initializes the SDRAM devices by issuing the following
memory command sequence:
■
■
■
■
■
■
■
■
■
Figure 3–17 on page 3–25
described below. The length of time between the reset and the first PCH command
should be 200 ms. This time can be reduced for simulation testing by setting the start-
up timer parameter in IP Toolbench.
1. A PCH command is sent to all banks by setting the precharge pin, the address bit
clk
NOP (for 200 ms, programmable)
PCH
Extended LMR (ELMR)
LMR
NOP (for 200 clock cycles, fixed)
PCH
ARF
ARF
LMR
a[10], or a[8] high.
0
200 clock cycles
P
0
[1]
1
1
0
L
0
[2]
0
L
[3]
shows a typical initialization timing sequence, which is
“DDR2 SDRAM Initialization Timing” on page
0
P
0
A
[4]
[5]
0
DDR and DDR2 SDRAM Controller Compiler User Guide
0
0
A
[5]
0 0
L L
[6]
3–26.
3–25