IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 96

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

B–2
DDR and DDR2 SDRAM Controller Compiler User Guide
f
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3. The DDR SDRAM device on the Nios Development Board, Cyclone II Edition, has
4. When you have made these settings, save the project and recompile the design in
These settings significantly increase the time required to compile the design in the
Quartus II software, but are likely to increase the f
5. On the Nios Development Board Cyclone II Edition (rev00 only), the DDR
For the correct connection of the ras and cas pins, refer to the Cyclone II 2C35
standard example design shipped with the Nios II Development Kit.
a minimum operating frequency of 77 MHz. So your design must have an f
greater than or equal to 77 MHz to use the DDR SDRAM. If a Quartus II
compilation of your system results in an f
following Quartus II optimizations to increase the f
a. Change the optimization technique to speed:
b. Turn on one-hot state machine processing:
c. Turn off multiplexer restructuring:
d. Turn on physical synthesis in the fitter:
the Quartus II software.
SDRAM pins ras and cas are accidentally switched on the PCB schematic. So to
maintain consistency between the PCB schematic and Quartus II pin assignments,
these two pins must also be switched in your Quartus II top-level design when
targeting the Nios Development Board, Cyclone II Edition (rev00 only).
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Choose Settings (Assignments menu).
Choose Analysis & Synthesis Settings.
In Optimization Technique, select Speed.
Choose Settings (Assignments menu).
Choose Analysis & Synthesis Settings.
For State Machine Processing, choose One-Hot.
Choose Settings (Assignments menu).
Choose Analysis & Synthesis Settings.
For Restructure Multiplexers, choose Off.
Choose Settings (Assignments menu).
Expand Fitter Settings by clicking the + symbol.
Choose Physical Synthesis Optimizations.
Turn on Perform physical synthesis for combinational logic.
Turn on Perform register duplication.
Turn on Perform register retiming.
For Physical synthesis effort, select Normal.
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less than 77 MHz, turn on some of the
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© March 2009 Altera Corporation
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