IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 38

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

3–2
Datapath
DDR and DDR2 SDRAM Controller Compiler User Guide
f
Table 3–1
Table 3–1. Bus Commands
The DDR and DDR2 SDRAM controllers must open SDRAM banks before they access
addresses in that bank. The row and bank to be opened are registered at the same time
as the active (ACT) command. The DDR and DDR2 SDRAM controllers close the bank
and open it again if they need to access a different row. The precharge (PCH)
command closes a bank.
The primary commands used to access SDRAM are read (RD) and write (WR). When
the WR command is issued, the initial column address and data word is registered.
When a RD command is issued, the initial address is registered. The initial data
appears on the data bus 2 to 3 clock cycles later (3 to 5 for DDR2 SDRAM). This delay
is the column address strobe (CAS) latency and is due to the time required to read the
internal DRAM core and register the data on the bus. The CAS latency depends on the
speed of the SDRAM and the frequency of the memory clock. In general, the faster the
clock, the more cycles of CAS latency are required. After the initial RD or WR
command, sequential reads and writes continue until the burst length is reached or a
burst terminate (BT) command is issued. DDR and DDR2 SDRAM devices support
burst lengths of 2, 4, or 8 data cycles. The auto-refresh command (ARF) is issued
periodically to ensure data retention. This function is performed by the DDR or DDR2
SDRAM controller.
The load mode register command (LMR) configures the SDRAM mode register. This
register stores the CAS latency, burst length, and burst type.
For more information, refer to the specification of the SDRAM that you are using.
The datapath provides the interface between the read and write data busses of the
local interface and the double-clocked, bidirectional data bus of the memory. The
local data busses are twice the width of the memory data bus width, because the DDR
or DDR2 SDRAM data interface transfers data on both the rising and falling edges of
the clock.
No operation
Active
Read
Write
Burst terminate
Precharge
Auto refresh
Load mode register
Command
shows the standard SDRAM bus commands.
Acronym
LMR
NOP
ACT
PCH
ARF
WR
RD
BT
ras_n
High
High
High
High
Low
Low
Low
Low
Chapter 3: Functional Description
© March 2009 Altera Corporation
cas_n
High
High
High
High
Low
Low
Low
Low
Block Description
we_n
High
High
High
High
Low
Low
Low
Low