IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 53

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 3: Functional Description
Device-Level Description
Figure 3–12. Testbench & Example Design
Table 3–5. Example Design & Testbench Files
© March 2009 Altera Corporation
<project name>_tb.v or .vhd
<project name>.v or .vhd
ddr_pll_<device family>.v or .vhd
ddr_fb_pll_stratixii.v or .vhd
<variation name>_example_driver.v or .vhd
<variation name> .v or .vhd
Notes to
(1) <project name> is the name of the IP Toolbench-generated example design.
(2) Replace <device family> with stratix for Stratix series, or cyclone for Cyclone series.
Table
test_complete
clock_source
3–5:
1
pnf
Filename
Figure 3–12
Ensure that the example driver is not optimized away in your example design, by
preserving the pnf output. Either attach it to a pin or assign it as a virtual pin in your
Quartus II project.
Table 3–5
testbench.
The example driver is a self-checking test generator for the DDR or DDR2 SDRAM
controller. It uses a state machine to write data patterns to a range of column
addresses, within a range of row addresses in all memory banks. It then reads back
the data from the same locations, and checks that the data matches. The pass not fail
(pnf) output transitions low if any read data fails the comparison. There is also a
pnf_per_byte output, which shows the comparison on a per byte basis. The
test_complete output transitions high for a clock cycle at the end of the write or
read sequence. After this transition the test restarts from the beginning.
The data patterns used are generated using an 8-bit LFSR per byte, with each LFSR
having a different initialization seed.
(1)
Testbench
(1)
Example Design
Example Driver
describes the files that are associated with the example design and the
(2)
shows the testbench and the example design.
PLL
Testbench for the example design.
Example design.
Example PLL.
Optional fed-back PLL (Stratix II devices only).
Example driver.
Top-level description of the custom MegaCore function.
DDR SDRAM Controller
DLL
DDR and DDR2 SDRAM Controller Compiler User Guide
Description
Bidrectional Board
Delay Model
DDR SDRAM
DIMM Model
3–17