IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 49

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 3: Functional Description
Device-Level Description
PLL Configurations
© March 2009 Altera Corporation
IP Toolbench creates up to two example PLLs in your project directory, which you can
parameterize to meet your exact requirements. IP Toolbench generates the example
PLLs with an input to output clock ratio of 1:1 and a clock frequency you entered in IP
Toolbench. In addition IP Toolbench sets the correct phase outputs on the PLLs’
clocks. You can edit the PLLs to meet your requirements with the ALTPLL
MegaWizard Plug-In. IP Toolbench overwrites your PLLs in your project directory
unless you turn off the Automatically generate the PLL option.
The external clocks are generated using standard I/O pins in DDR or DDR2 SDRAM
output mode (using the ALTDDIO_OUT megafunction). This generation matches the
way in which the write DQS is generated and allows better control of the skew
between the DDR or DDR2 SDRAM clock and the DQS to meet the t
of the SDRAM.
The PLL has the following outputs:
■
■
The PLL configuration differs for Stratix and Cyclone series.
The recommended configuration for implementing the DDR SDRAM controller in a
Stratix or Cyclone series is to use a single enhanced PLL to produce all the required
clock signals. No external clock buffer is required as the Altera device can generate
clk and clk# signals for DDR or DDR2 SDRAM devices.
The main difference between clock configurations is that Cyclone series do not have
the DQS phase shift reference circuit. Thus Cyclone series (and Stratix II devices) do
not need the additional dqs_ref_clk clock input, which drives this circuit.
In Cyclone II devices, an additional optional output (c2) is available. This output is
not normally required, unless IP Toolbench reports that a separate resynchronization
or postamble clock is required.
In Stratix series, the PLL has two other optional outputs. In most cases, these outputs
are not required. If you have chosen not to use DQS to capture your read data or if IP
Toolbench reports that a separate resynchronization or postamble clock is required,
the PLL includes the following IP Toolbench-recommended outputs:
■
■
These clocks are connected to the DDR or DDR2 SDRAM controller in the example
design file. If separate resynchronization or postamble clocks are not required, IP
Toolbench connects the resynchronization and postamble clock inputs on the
variation to the system or write clock as appropriate.
Output c0 drives the system clock that clocks most of the controller including the
state machine and the local interface. If the controller is being used in SOPC
Builder, this clock should drive the SOPC Builder generated module clock.
Output c1 drives the write data clock that lags the system clock by 270° and clocks
the write data and write data mask registers to offset them from the data strobe
signal.
Output c2 drives either the optional capture clock in non-DQS mode or an
optional separate resynchronization clock.
Output c3 drives the optional separate postamble clock.
DDR and DDR2 SDRAM Controller Compiler User Guide
DQSS
requirements
3–13