IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 69

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 3: Functional Description
Parameters
Table 3–12. Memory Property Parameters (Part 2 of 2)
Controller
Table 3–13. Local Interface
© March 2009 Altera Corporation
DQ bits per DQS pin
Use ×4 floorplan files that
include DM pins
Registered DIMM /
Unbuffered memory
Note to
(1) These are set by the device that you choose in the Presets list.
Local Interface
Table
Parameter
Parameter
3–12:
Table 3–13
Native or Avalon
Range
—
—
8
Range
shows the local interface options.
Units
Bits
—
—
Specifies the local side interface between the user logic and the memory
controller, refer to
This interface refers to the connection of the user logic (driver) to the
controller. There are few differences between the two interfaces in
performing read and write transactions. The Avalon-MM interface is
supported by SOPC builder (refer to the
For non-SOPC builder designs, you can build the driver logic to interface
to the controller with either the native interface (refer to
Description” on page
The number of data (DQ) bits for each data strobe (DQS) pin. This
option depend on the type of memory selected. Memories either
support ×4 or ×8 mode. Stratix II and Stratix III devices support
both modes. Cyclone III devices do not support the DQS mode, as
the devices do not have the DQS-related circuitry.
Two sets of recommended pins are provided for use with ×4
mode (four DQ per DQS) on the sides of Stratix II devices. If you
do not intend to use the memory DM pins, turn off this control to
give more available pins for your DDR SDRAM interface.
This option depends on the type of memory selected.
Select Registered DIMM for higher performance systems such as
servers, workstations, routers, and switches. To assure data
integrity, Registered DIMM uses additional devices: one to two
registers to latch address and command signals, and one PLL
clock buffer to adjust timing.
Registered DIMMs have their address and control lines buffered
on the DIMM to reduce signal loading. Because the registered
DIMM requires a buffer, they are more expensive than unbuffered
DIMMs. Unbuffered DIMMs do not buffer the address lines and
control lines, so they cost less and may be limited in the amount
the system may have installed because of system loading.
However an unbuffered DDR DIMM is able to operate one clock
cycle faster than a registered DIMM.
(Note 1)
“Interface Description” on page
3–19) or the Avalon-MM interface.
DDR and DDR2 SDRAM Controller Compiler User Guide
Description
Description
Avalon Interface Specifications).
3–19.
“Interface
3–33