PACCLK5406D-S-EVN Lattice, PACCLK5406D-S-EVN Datasheet - Page 10

• Manufacturer Part Number: PACCLK5406D-S-EVN
• Description: Development Software ispClock5312S Eval 56020A Dev Mix Sig
• Manufacturer: Lattice

Specifications of PACCLK5406D-S-EVN

• Tool Type: Development Software Support
• Core Architecture: CPLD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Invert Clock Output
This section describes the procedure to invert the ispClock5406D output. In this procedure you will use the
ispClock5406D Invert feature to invert Bank2 output.
To invert a clock output:
1. From the PAC-Designer schematic view, double-click the BANK_2+/BANK_2- Output Block.
Figure 10. Output Settings for BANK_2 & BANK_3
2. Choose Inverted = Yes from the BANK_2 section of the dialog and click OK.
3. Click the Download icon on the top toolbar.
4. Click OK.
5. Note the updated scope display.
The Output Settings for BANK_2 & BANK_3 dialog box appears.
PAC-Designer updates the output setting of the project.
The Frequency Summary dialog appears and reports the Reference and VCO frequency settings.
PAC-Designer reprograms the evaluation board with the updated JEDEC programming file.
The waveform shows the inverted BANK_2 output.
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ispClock5400D Evaluation Board
User’s Guide