PACCLK5406D-S-EVN Lattice, PACCLK5406D-S-EVN Datasheet - Page 5

• Manufacturer Part Number: PACCLK5406D-S-EVN
• Description: Development Software ispClock5312S Eval 56020A Dev Mix Sig
• Manufacturer: Lattice

Specifications of PACCLK5406D-S-EVN

• Tool Type: Development Software Support
• Core Architecture: CPLD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
2. Set DIP switches SW1 3 and 4 ON and all other switches OFF.
3. Start PAC-Designer.
4. Choose File > Open…
5. Browse the Base_Demo_CLK5406D.PAC project and choose Open.
Figure 2. ispClock5406D Schematic View
6. Choose File > Save As.
7. Specify File name: Base_Demo_CLK5406D_rev.PAC and click Save.
8. Choose View > ispCLK Output Summary.
Figure 3. Output Summary Sheet
The blue LOCK LED lights to indicate the on-chip PLL is stable and locked to a reference clock.
The Open dialog appears.
The ispPAC-CLK5406D schematic view appears.
The Save As dialog appears.
PAC-Designer creates a new revision of the project.
The Output Summary Sheet appears. The default demo will monitor the LVDS outputs driven by BANK_0 and
BANK_2.
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ispClock5400D Evaluation Board
User’s Guide