PACCLK5406D-S-EVN Lattice, PACCLK5406D-S-EVN Datasheet - Page 28

• Manufacturer Part Number: PACCLK5406D-S-EVN
• Description: Development Software ispClock5312S Eval 56020A Dev Mix Sig
• Manufacturer: Lattice

Specifications of PACCLK5406D-S-EVN

• Tool Type: Development Software Support
• Core Architecture: CPLD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
HCSL
HCSL termination involves a bias network to ground at the driver and no termination at the end of the T-Line.
Figure 32 shows the drivers biased through series resistors R16 and R17 (value of 33 ohms) combined with resis-
tors R19 and R20 (value of 50 ohms). R19 and R20 also provide T-Line source termination. The receiving end of
the T-Line does not require any termination. The sense resistors R28 and R29 (value 950 ohms) are not low
enough to serve as termination loads but, provide a way to view the waveforms on the scope. The scope input
impedance combined with R28 and R29 result in a 20:1 divider of the waveforms at the end of the T-Line.
Figure 32. Bank 0 HCSL with On-Board Termination
Power Supply Connections
The evaluation board is powered by a 12V to 5V power supply capable of providing one ampere or more. The
board can be powered either by a wall adapter with a 2.5mm coaxial power plug at J13 or from a bench supply with
banana plugs at J11 and J12. Once onboard, the supply is regulated (U2) to provide the 3.3V supply needed for
VCCD, VCCA, and VCCJ.
A second adjustable regulator (U3) provides the VCCO for banks 3 and 5 and it is programmable using the on-
board resistors and three of the DIP switches of SW1. To bypass the on-board regulators, zero ohm resistors R106
and R116 can be removed from the board to allow external supplies to power the ispClock5406D.
Troubleshooting
PAC-Designer 5.2: The ispClock5406D PLL Control dialog box of the ispClock5406D I
(ispClock_5406_I2C_Utility.exe) appears corrupted and the background color obscures the schematic
view.
To correct the display:
1. Exit the ispClock5406D I
2. From Windows, browse to the \PAC-Designer52\Macro folder of the PAC-Designer installation directory.
3. Locate the following files:
4. Rename each file so they appear as:
ispClock_5406_I2C_OutGroup_BI_Sch.emf
ispClock_5406_I2C_OutGroup_LI_Sch.emf
ispClock_5406_I2C_OutGroup_UI_Sch.emf
ispClock_5406_I2C_OutGroup_Sch.emf
ispClock_5406_I2C_PLL_Sch.emf
ispClock_5400_I2C_OutGroup_BI_Sch.emf
ispClock_5400_I2C_OutGroup_LI_Sch.emf
ispClock_5400_I2C_OutGroup_UI_Sch.emf
ispClock
Buffers
HCSL
R16
R17
33
33
R19
R20
50
50
2
ispClock5406D Standard Evaluation Board
C Utility.
50 ohms / 64.3 mm
5
0
On Board T-Line
On Board T-Line
o
h
m
s
/
6
4
3 .
m
m
R23
R24
0
0
28
R28
950
R29
950
BANK_0N
BANK_0P
R30
R31
0
0
J4
J3
ispClock5400D Evaluation Board
SMA to BNC Cable
SMA to BNC Cable
50 ohms / 91 cm
5
0
o
h
m
s
/
9
1
c
m
User’s Guide
Scope
5pF
5pF
50
50
2
C Utility