PACCLK5406D-S-EVN Lattice, PACCLK5406D-S-EVN Datasheet - Page 16
PACCLK5406D-S-EVN
Manufacturer Part Number
PACCLK5406D-S-EVN
Description
Development Software ispClock5312S Eval 56020A Dev Mix Sig
Manufacturer
Lattice
Datasheet
1.PACCLK5406D-S-EVN.pdf
(42 pages)
Specifications of PACCLK5406D-S-EVN
Tool Type
Development Software Support
Core Architecture
CPLD
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Lattice Semiconductor
Figure 17. Scope Plot - Skew Measurement
3. From the ispClock5406D I
Figure 18. ispClock5406D Output Group 1 Control
Note a small inherent skew of the outputs plus any set-up delay in cables is about 50-80ps.
The ispClock5406D Output Group 1 Control dialog appears.
The I
- V-Dividers settings/routing for each bank
- Phase-Skew enable
- Output Bank enable, OE control
2
C utility output group control supports in-system changes to:
2
C Utility click the Output Group 1 button.
16
ispClock5400D Evaluation Board
User’s Guide
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