PACCLK5406D-S-EVN Lattice, PACCLK5406D-S-EVN Datasheet - Page 2

• Manufacturer Part Number: PACCLK5406D-S-EVN
• Description: Development Software ispClock5312S Eval 56020A Dev Mix Sig
• Manufacturer: Lattice

Specifications of PACCLK5406D-S-EVN

• Tool Type: Development Software Support
• Core Architecture: CPLD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Introduction
Thank you for choosing the Lattice Semiconductor ispClock™ device family!
This guide describes how to start using the ispClock5400D Evaluation Board, an easy-to-use platform for evaluat-
ing and designing with the ispClock5406D in-system-programmable differential clock distribution device. The evalu-
ation board can be used stand-alone to review the performance and in-system programmability of the
ispClock5406D device or as a companion board and clock source for LatticeECP3™ FPGA evaluation boards:
• LatticeECP3 Serial Protocol Board
• LatticeECP3 Video Protocol Board
Please visit
documentation on each LatticeECP3 evaluation board.
About the ispClock5406D Device
This board features an ispClock5406D device that provides in-system-programmable zero delay universal fan-out
buffers for use in clock distribution applications. The on-board ispClock5406D is a 6-output clock distribution IC.
Differential ultra low skew outputs are organized with two banks per group. Each bank may be independently con-
figured to support separate I/O standards (LVDS, LVPECL, HSTL, SSTL, HCSL, and MLVDS) and output fre-
quency. In addition, each output provides independent programmable control of phase and time skew. All
configuration information is stored on-chip in non-volatile E
The ispClock5406D devices provide extremely low propagation delay (zero-delay) from input to output using the
on-chip low jitter high-performance phase locked loop (PLL). A set of four fixed dividers can be used to generate
four frequencies derived from the PLL clock. These dividers are designed in powers of 2 only (2, 4, 8, and 16). The
clock output from any of the V-dividers can then be routed to any clock output pair through the output routing
matrix. The output routing matrix also enables routing of reference clock inputs directly to any output. For additional
details, please refer to the
Note: Static electricity can severely shorten the lifespan of electronic components.
• Use anti-static precautions such as operating on an anti-static mat and wearing an anti-static wristband.
• Store the evaluation board in the anti-static packaging provided.
• Always touch the SMA connector housing to equalize voltage potential between yourself and the board.
Features
The ispClock5400D Evaluation Board package includes:
• ispClock5400D Evaluation Board – The board features the following on-board components and circuits:
• Pre-loaded Base Demo – The kit includes a pre-loaded demo design that highlights key performance character-
• Lattice ispDOWNLOAD™ Cable (HW-USBN-2A) – The ispDOWNLOAD cable provides a hardware connection
• User’s Guide – Provides information on powering, connecting lab equipment, and using the board as a clock
ispClock5406D programmable clock (ispPAC-CLK5406D-01SN48I)
istics of the ispClock5406D device.
for in-system programming of the ispClock5406D device.
– Crystal oscillator circuits
– Can oscillator circuit landing
– Resistor networks
– SMA connectors
– Power jack
– Test and JTAG interface headers
www.latticesemi.com/products/fpga/ecp3/ecp3evalboards
ispClock5400D Family Data
Sheet.
2
2
CMOS
®
memory.
for more information, demonstrations, and
ispClock5400D Evaluation Board
User’s Guide