PACCLK5406D-S-EVN Lattice, PACCLK5406D-S-EVN Datasheet - Page 7

• Manufacturer Part Number: PACCLK5406D-S-EVN
• Description: Development Software ispClock5312S Eval 56020A Dev Mix Sig
• Manufacturer: Lattice

Specifications of PACCLK5406D-S-EVN

• Tool Type: Development Software Support
• Core Architecture: CPLD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ispClock5400D Evaluation Board
Lattice Semiconductor
User’s Guide
Figure 6. Scope Plot - Four Differential Outputs
Note: For user-designed boards and other applications, refer to the data sheet configurations and the schematics
of Appendix A. The schematic shows different resistor combinations for the different output bank settings. In LVDS
mode the schematic uses a single 100 Ohm resistor between each BANK_P and BANK_N pin as a fully differential
output. The demo uses the default factory board assembly with zero Ohm resistors connecting the SMA terminals
directly to the output banks. This approach is for the demo only. Some of the waveforms displayed will only show
the positive side of each BANK output on the scope for simplicity and timing measurements.
Modify Clock Time Skew
This section describes the procedure to modify the time skew of the ispClock5406D output to eliminate the inherent
skew between output BANK_0 and BANK_2 due to device and cable parasitic.
To modify clock time skew:
1. Adjust the scope to display BANK0_P and BANK2_P signals only. Overlap the signals to compare the relative
skew.
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