MPC852TADS Freescale Semiconductor, MPC852TADS Datasheet - Page 37

• Manufacturer Part Number: MPC852TADS
• Description: Networking Modules & Development Tools ADS BOARD FOR 852
• Manufacturer: Freescale Semiconductor
• Type: Network Controller & Processorr

Specifications of MPC852TADS

• Memory Type: Flash, SDRAM
• Interface Type: RS-232, Ethernet, PCMCIA
• Operating Voltage: 1.8 V to 3.3 V
• Operating Temperature Range: 0 C to + 30 C
• Board Size: 233 mm x 150 mm
• Product: Modules
• For Use With/related Products: MPC852T
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

25
BR4
Compatible
Mode
OR4
Compatible
Mode
MPTPR
MAMR
MBMR
Register
a. Assuming 16.67 MHz BRGCLK.
b. Assuming 25MHz BRGCLK
c. For 66MHz BRGCLK
d. Assuming 32MHz BRGCLK.
TABLE 3-4. Memory Controller Initialization For 66Mhz with DRAM-EDO
K4S643232-TC60
All
supported
MB321BT08TASN60
MB322BT08TASN60
MB324CT00TBSN60
MB328CT00TBSN60
KS643232C-TC60
Device Type
Dram
Freescale Semiconductor, Inc.
For More Information On This Product,
SIMMs
OPERATING INSTRUCTIONS
Go to: www.freescale.com
030000C1
FFC00800
0400
40A21114
60A21114
C0A21114
20A21114
30A21114
60A21114
40B21114
60B21114
C0B21114
20B21114
30B21114
60B21114
D0802114
80802114
Init Value [hex]
MPC852TADS - User’s Manual
a
b
a
b
c
a
b
a
b
c
d
c
c
c
Base at 3000000, on UPMB
4 MB block size, all types access, initial address
multiplexing according to AMB.
Divide by 16 (decimal)
Refresh clock divided by 40
timer enabled. Type 2 address multiplexing scheme. 2
cycle disable timer. GPL4 disabled for data sampling
edge flexibility. 1 loop read. 1 loop write. 4 beats
refresh burst.
Refresh clock divided by 20
timer enabled. Type 2 address multiplexing scheme. 2
cycle disable timer. GPL4 disabled for data sampling
edge flexibility. 1 loop read. 1 loop write. 4 beats
refresh burst.
Refresh clock divided by 40
timer enabled. Type 3 address multiplexing scheme. 2
cycle disable timer. GPL4 disabled for data sampling
edge flexibility. 1 loop read. 1 loop write. 4 beats
refresh burst.
Refresh clock divided by 20
timer enabled. Type 3 address multiplexing scheme. 2
cycle disable timer. GPL4 disabled for data sampling
edge flexibility. 1 loop read. 1 loop write. 4 beats
refresh burst.
Refresh clock divided by D0 or 80. Periodic timer
enabled. Type 0 address multiplexing scheme. 2 cycle
disable timer. GPL4enabled. 1 loop read. 1 loop write.
4 beats refresh burst.
Description
a
a
a
a
or 60
or 60
or 30
or 30
Release 1.0
b
b
b
b
or C0
or C0
or 60
or 60
c
c
c
c
. Periodic
. Periodic
. Periodic
. Periodic