MPC852TADS Freescale Semiconductor, MPC852TADS Datasheet - Page 47

• Manufacturer Part Number: MPC852TADS
• Description: Networking Modules & Development Tools ADS BOARD FOR 852
• Manufacturer: Freescale Semiconductor
• Type: Network Controller & Processorr

Specifications of MPC852TADS

• Memory Type: Flash, SDRAM
• Interface Type: RS-232, Ethernet, PCMCIA
• Operating Voltage: 1.8 V to 3.3 V
• Operating Temperature Range: 0 C to + 30 C
• Board Size: 233 mm x 150 mm
• Product: Modules
• For Use With/related Products: MPC852T
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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A. Debug-Port Soft / Hard Resets are part of the development system and therefore bear mentioning.
B. In the 1:6.5 PLL operation the HRESET~ line drives the MODCK lines longer.
C. With respect to the ADS’s power-on defaults.
EPP negotiation mode.
4•1•5
On-board reset logic drives, with open-drain gates, the MPC’s HRESET* and SRESET* open-drain lines. Correct
operation of the internal reset sources of the MPC facilitates. As a rule, an internal reset source asserts HRESET* and
/ or SRESET* for a 512 system clock time minimum. With the exception of the Debug-Port Soft / Hard Resets
beyond the scope of this document to describe all the internal reset sources.
4•1•6
During reset the MPC device samples the state of some external pins in order to determine operational modes and pin
configurations. The MPC has 3 reset levels - each levels configurations are sampled:
4•1•6•1
The power-on reset configuration is sampled prior to the external logic’s negation of the PORESET. Included in this
configuration are pins, MODCK(1:2), that determine the MPC clock operation mode. The MPC852TADS supports
one clock modes:
4•1•6•2
When the RSTCONF* pin is asserted during a Hard Reset sequence, the MPC data bus is sampled in order to achieve
the MPC’s Hard Reset configuration. The reset configuration word is driven by the BCSR0 register whose defaults
are set during power-on reset. The BCSR0 drives half of the configuration word, i.e. data bits D(0:15) wherein the
reserved bits are designated as RSRVxx. It is possible to change
BCSR0 with new values. The configuration change becomes valid after Hard Reset has been applied to the MPC.
The RSTCONF* line on the ADS is always driven during Hard Reset. As consequent example being the MPC’s
internal Hard Reset configuration defaults become unusable.
The following system parameters act as the BCSR0 default address during power-on reset and, further, are character-
ized as being driven at Hard Reset.
1)
2)
3)
4)
5)
6)
Arbitration: internal arbitration is selected.
Interrupt Prefix: the internal default is the interrupt prefix at 0xFFF00000. It is overridden in order to pro-
vide an interrupt prefix, address 0, located within the DRAM.
Boot Disable: Boot is enabled.
Boot Port Size: a boot port size of 32-bit is selected.
Initial Internal Space Base: directly following Hard Reset the internal space is located at 0xFF000000.
Debug Pin Configuration: PCMCIA port B
MPC Internal Sources
Reset Configuration
1) Power-On Reset Configuration
2) Hard Reset Configuration
3) Soft Reset Configuration.
Power-On Reset Configuration
Hard Reset Configuration
1:6.5 PLL operation via an on-board clock generator.
In this mode MODCK(1:2) are driven with’10’ during
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Functional Description
MPC852TADS - User’s Manual
D
pins become PCMCIA port B pins.
C
the Hard Reset configuration by rewriting the
B
power-on reset.
Release 1.0
A
, it is