MPC852TADS Freescale Semiconductor, MPC852TADS Datasheet - Page 48

• Manufacturer Part Number: MPC852TADS
• Description: Networking Modules & Development Tools ADS BOARD FOR 852
• Manufacturer: Freescale Semiconductor
• Type: Network Controller & Processorr

Specifications of MPC852TADS

• Memory Type: Flash, SDRAM
• Interface Type: RS-232, Ethernet, PCMCIA
• Operating Voltage: 1.8 V to 3.3 V
• Operating Temperature Range: 0 C to + 30 C
• Board Size: 233 mm x 150 mm
• Product: Modules
• For Use With/related Products: MPC852T
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

36
D. In cases where PCMCIA port B pins exist.
A. At Hard Reset DSCK is configured to reside on the BDM Debug port - P12 or in Altera logic, when using on board
B. Capacitive load is dependant on the DRAM SIMM’s internal structure.
C. A valid address being one covered within a Chip-Select region.
D. Excepting SDRAM which is unbuffered.
E. Allows a configuration word, stored in Flash memory, to become active.
4•1•6•3
The SRESET* rising edge is used to configure the development port. Prior to the negation of SRESET*, the DSCK
is sampled in order to determine the debug mode enable / disable. After SRESET* negation, in the instance that the
debug mode was enabled, DSCK is again sampled for debug mode entry / non-entry.
DSDI is used to determine the debug port clock mode. DSDI is sampled after the negation of SRESET*.
The debug port controller, via on board command converter, provides the Soft Reset configuration. Option exists for
entering the debug mode directly.
4•2
Generated by a button, the ABORT (NMI) is the only external interrupt applied to the MPC via its interrupt controller.
When pressed, NMI input to the MPC is asserted. This interrupt type is meant to support the use of resident debuggers
made available to the ADS. MPC peripherals and the debug port generate all other MPC interrupts internally.
The IRQ0* line, routed as an NMI input, is driven by an open-drain gate in order to support external (off-board) NMI
generation. In order that external hardware may also drive this line, it is mandatory that the IRQ0* be driven by an
open-drain (or open-collector) gate.
4•3
Clocking the MPC on the MPC852TADS is done by using 10MHz Clock Generator Y2 connected to an EXTCLK
input. With 1:6.5 PLL mode (SW4[1-2] =’OFF,ON’), 66MHz of Clkout is achieved.
All MPC852TADS bus timings are referenced to the Clkout. Clkout signal drives all other clocks in the system, via
necessary buffering.
Use
250 ps) clock splitter - the CY2309ZC-1H, to split the load between all various clock consumers on board.
4•4
The ADS is also meant to serve as a hardware development platform. As such, it is necessary to buffer the MPC from
the local bus in order to avoid wasting its capacitive drive capability and, further, in order that the MPC remain avail-
able for off-board applications via the expansion connectors.
Buffers provide address and strobe lines while transceivers provide data. Since the capacitive load over DRAM
address lines may
buffers operated by 3.3V though 5V tolerant. The 74LVC buffer reduces board noise by reducing transition ampli-
tudes. Additional reductions in noise and reflection are made when a series of resistors is placed over a DRAM
address and strobe lines.
Data transceivers will open under two conditions: available access to a valid
configuration
to a valid board address exists. Avoiding such errors is the responsibility of the user.
command converter.
is
7)
8)
done with Crystal 3.3V zero delay buffer, which
Debug Port Pin Configuration: Debug port pins are located on the JTAG port.
External Bus Division Factor: internal to external clock frequencies are selected at a ratio of 1:1.
Soft Reset Configuration
Local Interrupter
Clock Generator
Buffering
E
. Consequently data conflicts are avoided when the off-board memory is read - provided no mapping
B
exceed 200 pF, the DRAM address lines are buffered separately. This is achieved with 74LVC
Freescale Semiconductor, Inc.
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Functional Description
MPC852TADS - User’s Manual
is
connected to 4 outputs, very low output to output skew (<
C D
board address or during Hard Reset
Release 1.0
A