MPC852TADS Freescale Semiconductor, MPC852TADS Datasheet - Page 42

• Manufacturer Part Number: MPC852TADS
• Description: Networking Modules & Development Tools ADS BOARD FOR 852
• Manufacturer: Freescale Semiconductor
• Type: Network Controller & Processorr

Specifications of MPC852TADS

• Memory Type: Flash, SDRAM
• Interface Type: RS-232, Ethernet, PCMCIA
• Operating Voltage: 1.8 V to 3.3 V
• Operating Temperature Range: 0 C to + 30 C
• Board Size: 233 mm x 150 mm
• Product: Modules
• For Use With/related Products: MPC852T
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

30
BR4
MPC86x
New Mode
OR4
MPC86x
New Mode
MPTPR
MAMR
MBMR
Register
a. BR3 is not initialized for MB321xx or MB324xx EDO DRAM SIMMs.
b. Assuming 16.67MHz BRGCLK
K4S643232-TC60
All
supported
MB321BT08TASN60
MB322BT08TASN60
MB324CT00TBSN60
MB328CT00TBSN60
KS643232C-TC60
TABLE 3-7. Memory Controller Initialization For 20Mhz
Device Type
Dram
Freescale Semiconductor, Inc.
For More Information On This Product,
SIMMs
OPERATING INSTRUCTIONS
Go to: www.freescale.com
0x000000C1
0xFC800A00
0400
60A21114
30A21114
60B21114
30B21114
42802114
Init Value [hex]
MPC852TADS - User’s Manual
b
Base at 0x0, on UPM B
4 MB block size, all types access, initial address
multiplexing according to AMB.
Divide by 16 (decimal)
Refresh clock divided by 60. Periodic timer enabled.
Type 2 address multiplexing scheme. 2 cycle disable
timer. GPL4 disabled for data sampling edge flexibility.
1 loop read. 1 loop write. 4 beats refresh burst.
Refresh clock divided by 30. Periodic timer enabled.
Type 2 address multiplexing scheme. 2 cycle disable
timer. GPL4 disabled for data sampling edge flexibility.
1 loop read. 1 loop write. 4 beats refresh burst.
Refresh clock divided by 60. Periodic timer enabled.
Type 3 address multiplexing scheme. 2 cycle disable
timer. GPL4 disabled for data sampling edge flexibility.
1 loop read. 1 loop write. 4 beats refresh burst.
Refresh clock divided by 30. Periodic timer enabled.
Type 3 address multiplexing scheme. 2 cycle disable
timer. GPL4 disabled for data sampling edge flexibility.
1 loop read. 1 loop write. 4 beats refresh burst.
Refresh clock divided by 42. Periodic timer enabled.
Type 0 address multiplexing scheme. 2 cycle disable
timer. GPL4 enabled. 1 loop read. 1 loop write. 4 beats
refresh burst.
Description
Release 1.0