MPC852TADS Freescale Semiconductor, MPC852TADS Datasheet - Page 49

• Manufacturer Part Number: MPC852TADS
• Description: Networking Modules & Development Tools ADS BOARD FOR 852
• Manufacturer: Freescale Semiconductor
• Type: Network Controller & Processorr

Specifications of MPC852TADS

• Memory Type: Flash, SDRAM
• Interface Type: RS-232, Ethernet, PCMCIA
• Operating Voltage: 1.8 V to 3.3 V
• Operating Temperature Range: 0 C to + 30 C
• Board Size: 233 mm x 150 mm
• Product: Modules
• For Use With/related Products: MPC852T
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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A. Peripherals and off-board.
B. After removal, the BCSR cannot be accessed unless power is reapplied to the ADS.
C. Data line contention is avoided during read cycles.
D. Normal being, for example, Single Read, Single Write, Burst Read & Burst Write.
E. Address multiplexing must take into account support for narrower bus widths.
4•5
The MPC memory controller is used as a chip-select generator in order to access on-board
board area. The latter cuts costs, lessens power consumption and increases flexibility. Off-board application develop-
ment may be enhanced by disabling memory modules (including the BCSRx) via BCSR1
memory connected via the expansion connectors. In this way, with the associated local memory disabled, a CS line
may be used off-board via the expansion connectors.
Local data transceivers do not open when a particular CS region has been disabled via BCSR1. This avoids possible
contention over data lines.
TABLE 4-1. "MPC852TADS Chip-Select Assignment"
memories / registers:
4•6
DRAM EDO is not supplied with the board. Users may place their own DRAM EDO on the U20 DRAM SIMM. The
MPC852TADS can operate with 4 MB of 60nsec delay EDO DRAM SIMM. Support is provided for the following:
5V powered FPM / EDO DRAM SIMM configured as 1M X32 up to 2 X 4M X 32 with 60 nsec or 70nsec delay.
All DRAM configurations are supported via the Board Control & Status Register (BCSR). For example, DRAM size
(4M to 32M) and delay (60 / 70 nsec) are read from BCSR2 and the associated registers (including the UPM) are
programmed accordingly.
DRAM timing control is performed by the MPC’s UPMA via the CS2 region or, in the instance of a dual-bank SIMM,
via region CS3. For example, RAS and CAS signal generation is performed using UPMA under the following condi-
tions: normal
to two in order to overcome the capacitive load on the DRAM SIMM RAS lines. Further, each is buffered from the
DRAM.
The DRAM module may be enabled / disabled at any time by writing DRAMEN~ bit in the BCSR1. See
Chip - Select Generator
DRAM
D
access; refresh cycles; and, during necessary address multiplexing
TABLE 4-1. MPC852TADS Chip-Select Assignment
Freescale Semiconductor, Inc.
For More Information On This Product,
CS0*
CS1*
CS2*
CS3*
CS4*
CS5*
CS(6-7)*
Chip Select:
a. If existent.
Go to: www.freescale.com
Functional Description
MPC852TADS - User’s Manual
Flash Memory
BCSR
DRAM Bank 1
DRAM Bank 2
SDRAM
Unused, user available
Unused, user available
outlines an MPC chip-select assignment for various ADS
Assignment
a
E
. CS2* and CS3* signals are split
B
A
in favour of an external
memories and reduce
Release 1.0
TABLE 4-
C