MPC852TADS Freescale Semiconductor, MPC852TADS Datasheet - Page 64

• Manufacturer Part Number: MPC852TADS
• Description: Networking Modules & Development Tools ADS BOARD FOR 852
• Manufacturer: Freescale Semiconductor
• Type: Network Controller & Processorr

Specifications of MPC852TADS

• Memory Type: Flash, SDRAM
• Interface Type: RS-232, Ethernet, PCMCIA
• Operating Voltage: 1.8 V to 3.3 V
• Operating Temperature Range: 0 C to + 30 C
• Board Size: 233 mm x 150 mm
• Product: Modules
• For Use With/related Products: MPC852T
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

52
9 - 10
11-12
4 - 5
7 - 8
BIT
A. MAIN power-on reset, i.e. when VDDH is powered to the MPC.
0
1
2
3
6
4•11•1
The BCSR0 is located at offset 0 on BCSR space, may be read or written at any time and has defaults set at the time
of MAIN
data contained in BCSR0 is driven on the data bus to provide the MPC’s Hard Reset configuration. The BCSR0 may
be written at any time in order to change the MPC’s Hard Reset configuration. The new values, regardless of the Hard
Reset source, become valid the next time a Hard Reset is issued to the MPC.
BCSR0 bits.
15) External (off-board) tool identification or software-option selection switch, SW5 status
16) Board Revision Code
ERB
IP
Reserved
BDIS
BPS(0:1)
Reserved
ISB(0:1)
DBGC(0:1)
DBPC(0:1)
A
MNEMONIC
power-on reset. If the Flash_Configuration_Enable~ bit in BCSR1 is inactive then, during Hard Reset,
BCSR0: Hard Reset Configuration Register
•
•
•
Channel Enable / Disable
PC Card VCC appliance
PC Card VPP appliance
Freescale Semiconductor, Inc.
External Arbitration. Arbitration is performed internally if’0’ during Hard
Reset. If’1’ during Hard Reset, Arbitration is performed externally.
Interrupt Prefix. Interrupt Prefix set to 0xFFF00000 if’0’ during Hard Reset.
If’1’ during Hard Reset, Interrupt Prefix set to 0.
Implemented
Boot Disable. CS0~ region is enabled for boot if’0’ during Hard-Reset. If’1’,
CS0~ region is disabled for boot.
Boot Port Size,’00’ - 32-bit,’01’ - 8-bit,’10’ - 16-bit,’11’ - reserved,
determines the CS0~ port size at boot.
Implemented
Initial Space Base. Initial base address of the internal MPC’s memory map
determined by the value at Hard Reset. If’00’, initial space at 0. If’01’, initial
space at 0x00F00000. If’10’, initial space at 0xFF000000. If’11’, initial space
at 0xFFF00000.
Debug Pin Configurations. PCMCIA channel II pin function’s determined
by the value during Hard Reset. If’00’ the pins function as PCMCIA channel
II pins. If’01’ the pins serve as Watch Points. If’10’ the pins are reserved.
If’11’ the pins become show-cycle attributes, e.g., VFLS, VF...
Debug Port Pin Configurations. Location of the debug port pins
determined by the value during Hard Reset. If’00’, debug port pins found on
the JTAG port. If’01’, the debug port is non-existent. If’10’, reserved. If’11’,
the debug port is on PCMCIA channel II pins.
For More Information On This Product,
TABLE 4-10. BCSR0 Description
Go to: www.freescale.com
Functional Description
a
a
MPC852TADS - User’s Manual
FUNCTION
TABLE 4-10.
provides a description of
Release 1.0
0
1
0
0
’00’
0
’10’
’00’
’00’
PON
DEF.
R,W
R,W
R,W
R,W
R,W
R,W
R,W
R,W
R,W
ATT