MPC852TADS Freescale Semiconductor, MPC852TADS Datasheet - Page 52

• Manufacturer Part Number: MPC852TADS
• Description: Networking Modules & Development Tools ADS BOARD FOR 852
• Manufacturer: Freescale Semiconductor
• Type: Network Controller & Processorr

Specifications of MPC852TADS

• Memory Type: Flash, SDRAM
• Interface Type: RS-232, Ethernet, PCMCIA
• Operating Voltage: 1.8 V to 3.3 V
• Operating Temperature Range: 0 C to + 30 C
• Board Size: 233 mm x 150 mm
• Product: Modules
• For Use With/related Products: MPC852T
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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As seen in
thereafter by another prescaler, the PTA (Periodic Timer A), with its dedicated UPM. When there is more than one
DRAM bank then refresh cycles are performed for consecutive banks resulting in faster refreshes. Below is the PTA
formula calculation:
Where:
As an example, a MCM36200 SIMM has the following data:
If these figures are assigned to the PTA formula then the PTA value should be 97 decimal or 61 hex.
4•6•4
Port width determines address line connection schemes. The number of address lines required for byte-selection
varies according to port width (1 for 16-bit port and 2 for 32-bit port) thus address connections to a memory port must
be changed if the width is changed. For example, a memory initially configured as a 32-bit port will have a list sig-
nificant (LS) address line connected to both the memory’s A0 line and the MPC’s A29 line. If the port is reconfigure
as a 16-bit port then the MPC’s LS address line becomes A30.
To maintain a linear
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BRG Clock
FIGURE 4-1
PTA: Periodic Timer A filed in MAMR. The value of the second divider.
Refresh_Period: time (usually in msec) required to refresh a DRAM bank.
Number_Of_Beats_Per_Refresh_Cycle: using the UPM looping capability, more than one refresh cycle
per refresh burst (up to 16) may be performed.
Number_Of_Rows_To_Refresh: number of rows in a DRAM bank.
T_BRG: cycle time of the BRG clock.
MPTPR: value of the PTP or Periodic Timer Prescaler (2 to 64).
Number_Of_Banks: number of DRAM banks to refresh.
Refresh_Period == 16 msec.
Number_Of_Beats_Per_Refresh_Cycle: 4 on the ADS.
Number_Of_Rows_To_Refresh == 1024.
T_BRG == 20 nsec (system clock @ 50 Mhz).
MPTPR: arbitrarily chosen to be 16.
Number_Of_Banks == 2 for that SIMM
PTA =
Variable Bus-Width Control
A
address scheme, all address lines connected to a memory must shift one bit. This shift involves
PTP
Refresh_Period X Number_Of_Beats_Per_Refresh_Cycle
Number_Of_Rows_To_Refresh X
above, the BRG clock is divided twice. Once by the PTP (Periodic Timer Prescaler) and
Freescale Semiconductor, Inc.
For More Information On This Product,
FIGURE 4-1 Refresh Scheme
Go to: www.freescale.com
Functional Description
MPC852TADS - User’s Manual
PTA
T_BRG
UPM
X MPTPR X Number_Of_Banks
DRAM BANKS
Release 1.0