MPC852TADS Freescale Semiconductor, MPC852TADS Datasheet - Page 55

• Manufacturer Part Number: MPC852TADS
• Description: Networking Modules & Development Tools ADS BOARD FOR 852
• Manufacturer: Freescale Semiconductor
• Type: Network Controller & Processorr

Specifications of MPC852TADS

• Memory Type: Flash, SDRAM
• Interface Type: RS-232, Ethernet, PCMCIA
• Operating Voltage: 1.8 V to 3.3 V
• Operating Temperature Range: 0 C to + 30 C
• Board Size: 233 mm x 150 mm
• Product: Modules
• For Use With/related Products: MPC852T
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

43
:
The Flash module may be disabled / enabled at any time by writing of’1’ /’0’ in the FlashEn~ bit in BCSR1.
4•8
Performance is enhanced, particularly at higher operation frequencies, by the board’s 8 MB of SDRAM. The SDRAM
is unbuffered from the MPC bus and then configured as 4 X 512K X 32 with Micron (or compatible)
MT48LC2M32B2
the fact that only one memory chip is involved, overall system performance is not affected.
The SDRAM doesn’t reside on a SIMM, rather it is soldered directly to the ADS pcb. The SDRAM may be enabled
/ disabled at any time by writing’1’ /’0’ to the SDRAM bit in BCSR1. See
page
SDRAM timing is controlled by the UPMB via its assigned CS line. See
Assignment" on page
CAS signals.
The SDRAM connection scheme is shown in
in
The selected SDRAM has 2048 rows and 256 columns thus necessitating eleven row and eight column address lines.
TABLE 4-6. on page 44
a 32-bit bus, one 32-bit SDRAM device is connected. Control is driven by the UPMB on the MPC852T thus the
SDRAM’s CS is interfaced to CS4 on the MPC852T. Any chip-select line that excludes CS0 is suitable. A utilized
SDRAM device’s DQM signals select byte lanes and connect to the appropriate MPC852T Byte Strobe (BS0:3)
signals. A10 SD connects to GPL0 as it has the functionality to either drive an address on the line or define a level.
This is required for A10 SD acts as both an address line and a control line. RAS and CAS are generated by GPL1 and
GPL2 respectively. The WE is generated by GPL3. CLK is driven by the MPC852T’s CLKOUT signal, a reference
point with respect to the MPC852T’s Memory Controller. The BS lines are connected to MPC lines A10 and A9 and
are used as high order address bits. Note in the table below that the numbering scheme of the MPC852T address lines
TABLE 4-8. on page
Flash Delay [nsec]
Read / Write
System Clock Frequency [MHz]
54.
a. Table figures refer to actual write access. Write operations continue internally and the device has
to be polled for operation completion.
Synchronous DRAM
a
Access [Clocks]
chips. Removing buffers eliminates the delay associated with address and data buffers. Due to
TABLE 4-5. Flash Memory Performance Figures
37. Unlike a regular DRAM, the synchronous DRAM has CS input in addition to RAS and
45.
below suggests a glueless interface between an MPC852T and the SDRAM. In the case of
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Functional Description
MPC852TADS - User’s Manual
FIGURE 4-4 on page 46
90
8
50
Number of System Clock Cycles
120
10
TABLE 4-1. "MPC852TADS Chip-Select
and the performance figures are available
TABLE 4-11. "BCSR1 Description" on
90
4
25
Release 1.0
120
5