ADUC7036BCPZ-RL Analog Devices Inc, ADUC7036BCPZ-RL Datasheet - Page 122

• Manufacturer Part Number: ADUC7036BCPZ-RL
• Description: Flash 96k ARM7 Dual 16-Bit ADC LIN I.C.
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7036BCPZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 48-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7036
Example LIN Hardware Synchronization Routine
Using the following C-source code LIN initialization routine,
LHSVAL1 begins to count on the first falling edge received on
the LIN bus. If LHSVAL1 exceeds the value written to LHSVAL1,
in this case 0x3F, a break compare interrupt is generated.
On the next falling edge, LHSVAL0 begins counting. LHSVAL0
monitors the number of falling edges and compares it to the
value written to LHSCON1[7:4]. In this example, the number of
edges to monitor is six falling edges of the LIN frame, or the five
void LIN_INIT(void )
{
RESETS AND
COUNTING
LHSVAL1
STARTS
char HVstatus;
GP2CON = 0x110000;
LHSCON0 = 0x1;
do{
}
while (!(HVstatus & 0x4)); // Transmit command is correct
while((LHSSTA & 0x20) == 0 )
{
}
LHSCON1 = 0x062;
LHSCON0 = 0x0114;
LHSVAL1 = 0x03F;
while((GP2DAT & 0x10 ) == 0 )
{}
LHSCON0 = 0x4;
IRQEN = 0x800;
LHSVAL1 = 0x3F
INTERRUPT IS
GENERATED
COMPARE
BREAK
HVDAT = 0x02; // Enable normal LIN Tx mode
HVCON = 0x08; // Write to Config0
do{
}
while(HVstatus & 0x1); // Wait until command is finished
LHSVAL0 STARTS
HVstatus = HVCON;
COUNTING
START
BIT
// Enable LHS on GPIO pins
// Reset LHS interface
// Wait until the LHS hardware is reset
// Sets stop edge as the fifth falling edge
// and the start edge as the first falling
// edge in the sync byte
// Gates UART Rx line, ensuring no interference
// from the LIN into the UART
// Selects the stop condition as a falling edge
// Enables generation of an interrupt on the
// stop condition
// Enables the interface
// Sets number of 131 kHz periods to generate a break interrupt
// 0x3F / 131 kHz ~ 480 μs, which is just over 9.5 Tbits
// Wait until LIN Bus returns high
// Enable LHS to detect Break Condition Ungate RX Line
// Disable all Interrupts except Break Compare Interrupt
// Enable UART Interrupt
// The UART is now configured and ready to be used for LIN
t
BIT
COUNTING AND A
STOP INTERRUPT
LHSVAL0 STOPS
IS GENERATED
Figure 52. Example LIN Configuration
Rev. C | Page 122 of 132
UART IS CONFIGURED,
DISABLED EXCEPT
BREAK COMPARE
LHS INTERRUPTS
falling edges of the sync byte. When this number of falling edges is
received, a stop condition interrupt is generated. It is at this point
that the UART is configured to receive the protected identifier.
The UART must be gated through LHSCON0[8] before the LIN
bus returns high. If the LIN bus returns high when UART is not
gated, UART communication errors may occur. This process is
shown in detail in Figure 52. Example code to ensure the success
of this process follows Figure 49.
STOP
BIT
START
BIT
RECEIVING DATA
VIA UART
BEGINS
ID0
ID1
ID2
ID3
ID4
ID5
P0
P1
STOP
BIT