ADUC7036BCPZ-RL Analog Devices Inc, ADUC7036BCPZ-RL Datasheet - Page 62

• Manufacturer Part Number: ADUC7036BCPZ-RL
• Description: Flash 96k ARM7 Dual 16-Bit ADC LIN I.C.
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7036BCPZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 48-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7036
SYSTEM CLOCKS
The ADuC7036 integrates a very flexible clocking system that
allows clock generation from one of three sources: an integrated
on-chip precision oscillator, an integrated on-chip low power
oscillator, or an external watch crystal. These three options are
shown in Figure 30.
Each of the internal oscillators is divided by 4 to generate a clock
frequency of 32.768 kHz. The PLL locks onto a multiple (625)
of 32.768 kHz, supplied by either of the internal oscillators or
the external crystal to provide a stable 20.48 MHz clock for the
system. The core can operate at this frequency or at a binary
submultiple of this frequency, thereby allowing power saving
when peak performance is not required.
By default, the PLL is driven by the low power oscillator that
generates a 20.48 MHz clock source. The ARM7TDMI core, in
OSCILLATOR
PRECISION
CLOCK
CORE
CORE CLOCK
PLL OUTPUT
(20.48MHz)
1
8
PLL LOCK
PRECISION
MCU
131kHz
2
DIV 4
CD
1
EXTERNAL
32.768kHz
SPI
PRECISION
32.768kHz
EXTERNAL CRYSTAL
CONTROLLER
PLL OUTPUT
(OPTIONAL)
CIRCUITRY
CRYSTAL
20.48MHz
PLLCON
FLASH
CORE CLOCK
PLL
Figure 30. System Clock Generation
LOW POWER
32.768kHz
LOW POWER
OSCILLATOR
Rev. C | Page 62 of 132
ECLK 2.5MHz
CLOCK
ADC
DIVIDER
CLOCK
LOW POWER
UART
131kHz
ADCMDE
DIV 4
ADC
turn, is driven by a clock divider (set by the CD bits in the
POWCON register). By default, the CD bits are configured to
divide the PLL output by 2, thereby generating a core clock of
10.24 MHz. The divide factor can be modified to generate a
binary-weighted divider factor in the range of 1 to 128 that can
be altered dynamically by user code.
The ADC is driven by the output of the PLL, which is divided to
provide an ADC clock source of 512 kHz. In low power mode,
the ADC clock source is switched from the standard 512 kHz to
the low power 131 kHz oscillator.
Note that the low power oscillator drives both the watchdog and
core wake-up timers through a divide-by-4 circuit. A detailed
block diagram of the ADuC7036 clocking system is shown in
Figure 30.
CORE CLOCK
CORE CLOCK
CORE CLOCK
CORE CLOCK
OSCILLATOR
LOW POWER
LOW POWER
LOW POWER
LOW POWER
LOW POWER
LOW POWER
LOW POWER
PLL OUTPUT
PRECISION
EXTERNAL
EXTERNAL
PRECISION
EXTERNAL
PRECISION
32.768kHz
32.768kHz
32.768kHz
32.768kHz
32.768kHz
32.768kHz
32.768kHz
32.768kHz
32.768kHz
32.768kHz
32.768kHz
GPIO_5
GPIO_8
131kHz
(5MHz)
GENERAL-PURPOSE
SYNCHRONIZATION
HIGH ACCURCY
CALIBRATION
CALIBRATION
LOW POWER
WATCHDOG
COUNTER
COUNTER
WAKE-UP
LIFETIME
LIN H/W
TIMER0
TIMER1
TIMER2
TIMER3
TIMER4
STI