ADUC7036BCPZ-RL Analog Devices Inc, ADUC7036BCPZ-RL Datasheet - Page 126

• Manufacturer Part Number: ADUC7036BCPZ-RL
• Description: Flash 96k ARM7 Dual 16-Bit ADC LIN I.C.
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7036BCPZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 48-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7036
BSD COMMUNICATION FRAME
To transfer data between a master and slave, or vice versa, the
construction of a BSD frame is required. A BSD frame contains
seven key components: pause/sync, a direction (DIR) bit, the
slave address, the register address, data, parity bits (P1 and P2),
and the acknowledge bit from the slave.
If the master is transmitting data, all bits except the acknowledge
bit are transmitted by the master.
If the master is requesting data from the slave, the master transmits
the pause/sync, direction bit, slave address, register address, and
P1. The slave then transmits the data bytes, the P2 bit, and the
acknowledge bit in the following sequence:
1.
2.
3.
4.
5.
6.
7.
8.
The acknowledge bit is always transmitted by the slave to
indicate whether the information was received or transmitted.
Table 96. BSD Protocol Description
Pause
3 bits
BSD Example Pulse Widths
An example of the different pulse widths is shown in Figure 54.
For each bit, the period for which the bus is held low defines
what type of bit it is. If the bit is a sync bit, the pulse is held low
for one bit. If the bit is 0, the pulse is held low for three bits. If
the bit is 1, the pulse is held low for six bits.
Pause: ≥ three synchronization pulses
DIR: signifies the direction of data transfer
DIR = 0 if master sends request
DIR = 1 if slave sends request
Slave address
Register address: defines register to be read or written
Bit 3 is set to write and cleared to read
Data: 8-bit read only receive register
P1 and P2
P1 = 0 if even number of 1s in eight previous bits
P1 = 1 if odd number of 1s in eight previous bits
P2 = 0 if even number of 1s in data-word
P2 = 1 if odd number of 1s in data-word
Acknowledge bit
ACK = 0 if transmission is successful
DIR
1 bit
Slave
Address
3 bits
Register
Address
4 bits
P1
1 bit
Data
8 bits
P2
1 bit
Rev. C | Page 126 of 132
ACK
1 bit
If the master is transmitting data, the signal is held low for the
duration of the signal by the master. An example of a master
transmitting a 0 is shown in Figure 55. If the slave is
transmitting data, the master pulls the bus low to begin
communication. The slave must pull the bus low before t
elapses and then hold the bus low until either t
after which time the bus is released by the slave. An example of a
slave transmitting a 0 is shown in Figure 56.
Typical BSD Program Flow
Because BSD is a PWM communication protocol controlled by
software, the user must construct the required data from each bit.
For example, in constructing the slave address, the slave node
receives the three bits and the user constructs the relevant address.
When BSD communication is initiated by the master, data is
transmitted and received by the slave node. A flowchart showing
this process is shown in Figure 57.
BUS PULLED LOW
BY MASTER
BUS PULLED LOW
BY MASTER
t
SYNC
t
t
0
1
t
t
SYNC
SYNC
Figure 55. BSD Master Transmitting a 0
Figure 56. BSD Slave Transmitting a 0
t
t
0
0
Figure 54. BSD Bit Transmission
BUS HELD LOW
BY SLAVE
RELEASED BY
MASTER
BUS RELEASED BY
MASTER AFTER
BUS RELEASED BY
SLAVE AFTER
0
t
or t
0
t
0
1
has elapsed,
SYNC