ADUC7036BCPZ-RL Analog Devices Inc, ADUC7036BCPZ-RL Datasheet - Page 26

• Manufacturer Part Number: ADUC7036BCPZ-RL
• Description: Flash 96k ARM7 Dual 16-Bit ADC LIN I.C.
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7036BCPZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 48-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7036
The FEE0CON and FEE1CON Registers section to the FEE0MOD and FEE1MOD Registers section provide detailed descriptions of the
bit designations for each of the Flash/EE control MMRs.
FEE0CON and FEE1CON Registers
Name: FEE0CON and FEE1CON
Address: 0xFFFF0E08 and 0xFFFF0E88
Default Value: 0x07
Access: Read/write access
Function: These 8-bit registers are written by user code to control the operating modes of the Flash/EE memory controllers for Block 0
(32 kB) and Block 1 (64 kB).
Table 13. Command Codes in FEE0CON and FEE1CON
Code
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
1
2
The x represents 0 or 1, designating Flash/EE Block 0 or Block 1.
The FEE0CON register reads 0x07 immediately after the execution of this command.
2
2
2
2
2
2
2
Command
Reserved
Single read
Single write
Erase write
Single verify
Single erase
Mass erase
Reserved
Reserved
Reserved
Signature
Protect
Reserved
Reserved
Ping
Description
Reserved. This command should not be written by user code.
Load FEExDAT with the 16-bit data indexed by FEExADR.
Write FEExDAT at the address pointed by FEExADR. This operation takes 50 μs.
Erase the page indexed by FEExADR and write FEExDAT at the location pointed by FEExADR. This operation takes 20 ms.
Compare the contents of the location pointed by FEExADR to the data in FEExDAT. The result of the comparison is
returned in FEExSTA, Bit 1 or Bit 0.
Erase the page indexed by FEExADR.
Erase Block 0 (32 kB) or Block 1 (64 kB) of user space. The 2 kB kernel is protected. This operation takes 1.2 sec. To
prevent accidental execution, a command sequence is required to execute this instruction (see the Command
Sequence for Executing a Mass Erase section).
Default command.
Reserved. This command should not be written by user code.
Reserved. This command should not be written by user code.
Reserved. This command should not be written by user code.
FEE0CON: This command results in the generation of a 24-bit linear feedback shift register (LFSR)-based signature
that is loaded into FEE0SIG.
If FEE0ADR is less than 0x97800, this command results in a 24-bit LFSR-based signature of the user code space from
the page specified in FEE0ADR upwards, including the kernel, security bits, and Flash/EE key.
If FEE0ADR is greater than 0x97800, the kernel and manufacturing data are signed. This operation takes 120 μs.
FEE1CON: This command results in the generation of a 24-bit LFSR-based signature, beginning at FEE1ADR and
ending at the end of the 63,500 block, that is loaded into FEE1SIG. The last page of this block is not included in the
sign generation.
This command can be run only once. The value of FEExPRO is saved and can be removed only with a mass erase
(0x06) or with the software protection key.
Reserved. This command should not be written by user code.
Reserved. This command should not be written by user code.
No operation, interrupt generated.
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