ADUC7036BCPZ-RL Analog Devices Inc, ADUC7036BCPZ-RL Datasheet - Page 57

• Manufacturer Part Number: ADUC7036BCPZ-RL
• Description: Flash 96k ARM7 Dual 16-Bit ADC LIN I.C.
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7036BCPZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 48-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

In ADC normal power mode, the maximum ADC throughput
rate is 8 kHz. This is configured by setting the SF and AF bits in
the ADCFLT MMR to 0, with all other filtering options disabled.
As a result, 0x0000 is written to ADCFLT. Figure 24 shows a
typical 8 kHz filter response based on these settings.
A modified version of the 8 kHz filter response can be configured
by setting the running average bit (ADCFLT[14]). As a result,
an additional running-average-by-two filter is introduced on all
ADC output samples, which further reduces the ADC output
noise. In addition, by maintaining an 8 kHz ADC throughput
rate, the ADC settling time is increased by one full conversion
period. The modified frequency response for this configuration
is shown in Figure 25.
At very low throughput rates, the chop enable bit in the
ADCFLT register can be enabled to minimize offset errors and,
more importantly, temperature drift in the ADC offset error.
With chop enabled, there are two primary variables (Sinc3
decimation factor and averaging factor) available to allow the
user to select an optimum filter response, but there is a trade-off
between filter bandwidth and ADC noise.
Figure 24. Typical Digital Filter Response at f
Figure 25. Typical Digital Filter Response at f
–100
–100
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
0
0
0
2
2
4
4
6
6
8
8
FREQUENCY (kHz)
FREQUENCY (kHz)
10
10
12
12
14
14
ADC
ADC
= 8 kHz (ADCFLT = 0x0000)
= 8 kHz (ADCFLT = 0x4000)
16
16
18
18
20
20
22
22
24
24
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For example, with the chop enable bit (ADCFLT[15]) set to 1,
the SF value (ADCFLT[6:0]) increases to 0x1F (31 decimal) and
an AF value (ADCFLT[13:8]) of 0x16 (22 decimal) is selected,
resulting in an ADC throughput of 10 Hz. The frequency
response in this case is shown in Figure 26.
Changing SF to 0x1D and setting AF to 0x3F with the chop enable
bit still enabled configures the ADC with its minimum throughput
rate of 4 Hz in normal mode. The digital filter frequency response
with this configuration is shown in Figure 27.
In ADC low power mode, the Σ-Δ modulator clock of the ADC
is no longer driven at 512 kHz, but is driven directly from the
on-chip, low power, 131 kHz oscillator. Subsequently, if normal
mode is used for the same ADCFLT configuration, all filter values
should be scaled by a factor of approximately 4. Therefore, it is
possible to configure the ADC for 1 Hz throughput in low power
mode. The filter frequency response for this configuration is shown
in Figure 28.
Figure 26. Typical Digital Filter Response at f
Figure 27. Typical Digital Filter Response at f
–100
–100
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
0
0
0
20
40
60
20
FREQUENCY (kHz)
FREQUENCY (kHz)
80
100
120
ADC
ADC
= 10 Hz (ADCFLT = 0x961F)
= 4 Hz (ADCFLT = 0xBF1D)
40
140
160
ADuC7036
180
200
6
0