CY7C68053-56BAXIT Cypress Semiconductor Corp, CY7C68053-56BAXIT Datasheet - Page 11

• Manufacturer Part Number: CY7C68053-56BAXIT
• Description: CY7C68053-56BAXIT
• Manufacturer: Cypress Semiconductor Corp
• Series: MoBL-USB™r

Specifications of CY7C68053-56BAXIT

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: CY7C680xx
• Ram Size: 16K x 8
• Interface: I²C, USB
• Number Of I /o: 56
• Voltage - Supply: 1.71 V ~ 1.89 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-VFBGA
• Processor Series: CY7C68xx
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 24
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3687 - KIT DEV MOBL-USB FX2LP18
• Lead Free Status / Rohs Status: Details

Table 6. Strap Boot EEPROM Address Lines to These
Values
3.18.2 I
At power on reset the I
VID/PID/DID and configuration bytes and up to 16 kBytes of
Document # 001-06120 Rev *J
Note
16
128
256
4K
8K
16K
8. This EEPROM does not have address pins.
Bytes
2
C Interface Boot Load Access
24AA00
24AA01
24AA02
24AA32
24AA64
24AA128
Example EEPROM
[8]
2
C interface boot loader loads the
XTALIN
XTALOUT
RESET#
WAKEUP#
SCL
SDA
IFCLK
CLKOUT
DPLUS
DMINUS
Figure 6. Signals
N/A
A2
Port
0
0
0
0
0
N/A
A1
0
0
0
0
0
INT0#/PA0
INT1#/PA1
WU2/PA3
N/A
A0
0
0
1
1
1
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PA2
PA4
PA5
PA6
PA7
GPIF Master
RDY0
RDY1
CTL0
CTL1
CTL2
INT0#/PA0
INT1#/PA1
PA2
WU2/PA3
PA4
PA5
PA6
PA7
FD[15]
FD[14]
FD[13]
FD[12]
FD[11]
FD[10]
FD[9]
FD[8]
FD[7]
FD[6]
FD[5]
FD[4]
FD[3]
FD[2]
FD[1]
FD[0]
program/data. The available RAM spaces are 16 kBytes from
0x0000–0x3FFF and 512 bytes from 0xE000–0xE1FF. The 8051
is reset. I
3.18.3 I
The 8051 can control peripherals connected to the I
the I2CTL and I2DAT registers. FX2LP18 provides I
control only, it is never an I
4. Pin Assignments
Figure 6
pin diagram.Three modes are available: Port, GPIF master, and
Slave FIFO. These modes define the signals on the right edge
of the diagram. The 8051 selects the interface mode using the
IFCONFIG[1:0] register bits. Port mode is the power on default
configuration.
2
identifies all signals for the package. It is followed by the
2
C Interface General Purpose Access
C interface boot loads only occur after power on reset.
Slave FIFO
FD[15]
FD[14]
FD[13]
FD[12]
FD[11]
FD[10]
FD[9]
FD[8]
FD[7]
FD[6]
FD[5]
FD[4]
FD[3]
FD[2]
FD[1]
FD[0]
SLRD
SLWR
FLAGA
FLAGB
FLAGC
INT0#/PA0
INT1#/PA1
SLOE
WU2/PA3
FIFOADR0
FIFOADR1
PKTEND
PA7/FLAGD/SLCS#
2
C slave.
CY7C68053
Page 11 of 42
2
C bus using
2
C master
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