CY7C68053-56BAXIT Cypress Semiconductor Corp, CY7C68053-56BAXIT Datasheet - Page 26

CY7C68053-56BAXIT

CY7C68053-56BAXIT

Manufacturer Part Number
CY7C68053-56BAXIT
Description
CY7C68053-56BAXIT
Manufacturer
Cypress Semiconductor Corp
Series
MoBL-USB™r
Datasheet

Specifications of CY7C68053-56BAXIT

Applications
USB Microcontroller
Core Processor
8051
Program Memory Type
ROMless
Controller Series
CY7C680xx
Ram Size
16K x 8
Interface
I²C, USB
Number Of I /o
56
Voltage - Supply
1.71 V ~ 1.89 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
56-VFBGA
Processor Series
CY7C68xx
Core
8051
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
I2C
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
24
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
CY3687 - KIT DEV MOBL-USB FX2LP18
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C68053-56BAXIT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
8
Table 11. GPIF Synchronous Signals Parameters with Externally Sourced IFCLK
9.3 Slave FIFO Synchronous Read
Table 12. Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK
Document # 001-06120 Rev *J
Notes
t
t
t
t
t
t
t
t
t
t
t
t
t
t
16. Dashed lines denote signals with programmable polarity.
17. GPIF asynchronous RDY
IFCLK
SRY
RYH
SGD
DAH
XGD
XCTL
IFCLK
SRD
RDH
OEon
OEoff
XFLG
XFD
18. IFCLK must not exceed 48 MHz.
Parameter
Parameter
Figure 9. Slave FIFO Synchronous Read Timing Diagram
IFCLK period
RDY
Clock to RDY
GPIF data to clock setup time
GPIF data hold time
Clock to GPIF data output propagation delay
Clock to CTL
IFCLK period
SLRD to clock setup time
Clock to SLRD hold time
SLOE turn-on to FIFO data valid
SLOE turn-off to FIFO data hold
Clock to FLAGS output propagation delay
Clock to FIFO data output propagation delay
x
signals have a minimum setup time of 50 ns when using internal 48 MHz IFCLK.
X
to clock setup time
FLAGS
SLOE
SLRD
DATA
IFCLK
X
[18]
X
output propagation delay
Description
Description
t
OEon
N
t
SRD
t
IFCLK
t
RDH
t
XFLG
t
XFD
N+1
[16]
20.83
20.83
18.7
2.15
Min
Min
2.9
3.7
3.2
4.5
0
[17]
t
OEoff
[17]
13.06
Max
Max
10.5
10.5
200
9.5
15
11
CY7C68053
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Page 26 of 42
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