CY7C68053-56BAXIT Cypress Semiconductor Corp, CY7C68053-56BAXIT Datasheet - Page 7

• Manufacturer Part Number: CY7C68053-56BAXIT
• Description: CY7C68053-56BAXIT
• Manufacturer: Cypress Semiconductor Corp
• Series: MoBL-USB™r

Specifications of CY7C68053-56BAXIT

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: CY7C680xx
• Ram Size: 16K x 8
• Interface: I²C, USB
• Number Of I /o: 56
• Voltage - Supply: 1.71 V ~ 1.89 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-VFBGA
• Processor Series: CY7C68xx
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 24
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3687 - KIT DEV MOBL-USB FX2LP18
• Lead Free Status / Rohs Status: Details

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Figure 3. FX2LP18 Internal Code Memory
3.10 Program/Data RAM
This section describes the FX2LP18 RAM.
3.10.1 Size
The FX2LP18 has 16 kBytes of internal program/data RAM. No
USB control registers appear in this space.
Memory maps are shown in
3.10.2 Internal Code Memory
This mode implements the internal 16-kByte block of RAM
(starting at 0) as combined code and data memory. Only the
internal 16 kBytes and scratch pad 0.5 kBytes RAM spaces
have the following access:
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Document # 001-06120 Rev *J
CTL0-2. If tri-stated via GPIFIDLECTL, these pins must be
pulled to V
RESET#, WAKEUP#. These pins must be pulled to V
GND or driven by another chip during suspend.
USB download
USB upload
Setup data pointer
I
2
C interface boot load
FFFF
E200
E1FF
E000
CC_IO
3FFF
0000
Data
4K FIFO buffers
0.5 kBytes RAM
16 kBytes RAM
Code and Data
or GND or driven by another chip.
7.5 kBytes
USB regs and
.
.
.
Figure 3
and
Figure
4.
CC_IO
or
3.11 Register Addresses
3.12 Endpoint RAM
This section describes the FX2LP18 Endpoint RAM.
3.12.1 Size
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3.12.2 Organization
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3.12.3 Setup Data Buffer
A separate 8-byte buffer at 0xE6B8-0xE6BF holds the setup data
from a CONTROL transfer.
Figure 4. Register Address Memory
3 × 64 bytes (Endpoints 0, 1)
8 × 512 bytes (Endpoints 2, 4, 6, 8)
EP0
Bidirectional endpoint zero, 64-byte buffer
EP1IN, EP1OUT
64-byte buffers: bulk or interrupt
EP2, 4, 6, 8
Eight 512-byte buffers: bulk, interrupt, or isochronous. EP4 and
EP8 can be double buffered, while EP2 and 6 can be double,
triple, or quad buffered. For high speed endpoint configuration
options, see
FFFF
F000
EFFF
E800
E1FF
E7FF
E7C0
E780
E77F
E740
E700
E6FF
E500
E4FF
E47F
E400
E3FF
E000
E7BF
E73F
E480
E200
128 Bytes GPIF Waveforms
8051 Addressable Registers
2 kBytes RESERVED
64 Bytes EP0 IN/OUT
Figure 5 on page
64 Bytes RESERVED
Reserved (512)
4 kBytes EP2-EP8
64 Bytes EP1OUT
64 Bytes EP1IN
Reserved (128)
8051 xdata RAM
512 Bytes
(8 x 512)
buffers
(512)
8.
CY7C68053
Page 7 of 42
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