DSPIC33FJ256GP710A-H/PT Microchip Technology, DSPIC33FJ256GP710A-H/PT Datasheet - Page 137
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DSPIC33FJ256GP710A-H/PT
Manufacturer Part Number
DSPIC33FJ256GP710A-H/PT
Description
16 Bit MCU/DSP 100LD 40MIPS 256KB FLASH 100 TQFP 12x12x1mm TRAY
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheet
1.DSPIC33FJ64GP206A-IMR.pdf
(338 pages)
Specifications of DSPIC33FJ256GP710A-H/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
30K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 32x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 140°C
Package / Case
100-TQFP
Processor Series
dsPIC33F
Core
dsPIC
Data Bus Width
16 bit
Interface Type
SPI, I2C, UART, JTAG
Number Of Programmable I/os
35
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 140 C
Mounting Style
SMD/SMT
Development Tools By Supplier
MPLAB IDE Software
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
A/d Bit Size
10 bit
A/d Channels Available
13
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ256GP710A-H/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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8.0
Direct Memory Access (DMA) is a very efficient
mechanism of copying data between peripheral SFRs
(e.g., UART Receive register, Input Capture 1 buffer),
and buffers or variables stored in RAM, with minimal
CPU
automatically copy entire blocks of data without
requiring the user software to read or write the
peripheral Special Function Registers (SFRs) every
time a peripheral interrupt occurs. The DMA controller
uses a dedicated bus for data transfers and therefore,
does not steal cycles from the code execution flow of
the CPU. To exploit the DMA capability, the
corresponding user buffers or variables must be
located in DMA RAM.
The dsPIC33FJXXXGPX06A/X08A/X10A peripherals
that can utilize DMA are listed in Table 8-1 along with
their associated Interrupt Request (IRQ) numbers.
2009 Microchip Technology Inc.
Note 1: This data sheet summarizes the features
intervention.
2: Some registers and associated bits
DIRECT MEMORY ACCESS
(DMA)
of
X10A family of devices. However, it is not
intended to be a comprehensive refer-
ence source. To complement the informa-
tion in this data sheet, refer to Section
22. “Direct Memory Access (DMA)”
(DS70182) in the “dsPIC33F/PIC24H
Family Reference Manual”, which is avail-
able from the Microchip web site
(www.microchip.com).
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
the dsPIC33FJXXXGPX06A/X08A/
The
dsPIC33FJXXXGPX06A/X08A/X10A
DMA
controller
can
Preliminary
TABLE 8-1:
The DMA controller features eight identical data
transfer channels.
Each channel has its own set of control and status reg-
isters. Each DMA channel can be configured to copy
data either from buffers stored in dual port DMA RAM
to peripheral SFRs, or from peripheral SFRs to buffers
in DMA RAM.
The DMA controller supports the following features:
• Word or byte sized data transfers.
• Transfers from peripheral to DMA RAM or DMA
• Indirect Addressing of DMA RAM locations with or
• Peripheral Indirect Addressing – In some
• One-Shot Block Transfers – Terminating DMA
• Continuous Block Transfers – Reloading DMA
• Ping-Pong Mode – Switching between two DMA
• Automatic or manual initiation of block transfers
• Each channel can select from 20 possible
For each DMA channel, a DMA interrupt request is
generated when a block transfer is complete. Alterna-
tively, an interrupt can be generated when half of the
block has been filled.
INT0
Input Capture 1
Input Capture 2
Output Compare 1
Output Compare 2
Timer2
Timer3
SPI1
SPI2
UART1 Reception
UART1 Transmission
UART2 Reception
UART2 Transmission
ADC1
ADC2
DCI
ECAN1 Reception
ECAN1 Transmission
ECAN2 Reception
ECAN2 Transmission
RAM to peripheral.
without automatic post-increment.
peripherals, the DMA RAM read/write addresses
may be partially derived from the peripheral.
transfer after one block transfer.
RAM buffer start address after every block
transfer is complete.
RAM start addresses between successive block
transfers, thereby filling two buffers alternately.
sources of data sources or destinations.
Peripheral
PERIPHERALS WITH DMA
SUPPORT
DS70593B-page 137
IRQ Number
10
33
12
30
31
13
21
60
34
70
55
71
11
0
1
5
2
6
7
8
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