DSPIC33FJ256GP710A-H/PT Microchip Technology, DSPIC33FJ256GP710A-H/PT Datasheet - Page 296
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DSPIC33FJ256GP710A-H/PT
Manufacturer Part Number
DSPIC33FJ256GP710A-H/PT
Description
16 Bit MCU/DSP 100LD 40MIPS 256KB FLASH 100 TQFP 12x12x1mm TRAY
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheet
1.DSPIC33FJ64GP206A-IMR.pdf
(338 pages)
Specifications of DSPIC33FJ256GP710A-H/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
30K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 32x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 140°C
Package / Case
100-TQFP
Processor Series
dsPIC33F
Core
dsPIC
Data Bus Width
16 bit
Interface Type
SPI, I2C, UART, JTAG
Number Of Programmable I/os
35
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 140 C
Mounting Style
SMD/SMT
Development Tools By Supplier
MPLAB IDE Software
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
A/d Bit Size
10 bit
A/d Channels Available
13
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ256GP710A-H/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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- Download datasheet (3Mb)
dsPIC33FJXXXGPX06A/X08A/X10A
TABLE 25-34: DCI MODULE (MULTI-CHANNEL, I
DS70593B-page 296
AC CHARACTERISTICS
CS10
CS11
CS20
CS21
CS30
CS31
CS35
CS36
CS40
CS41
CS50
CS51
CS55
CS56
Note 1:
Param
No.
2:
3:
4:
T
T
T
T
T
T
T
T
T
T
T
T
T
T
Symbol
CSCKL
CSCKH
CSCKF
CSCKR
CSDOF
CSDOR
CSDI
COFSF
COFSR
SCOFS
DV
DIV
HCSDI
HCOFS
These parameters are characterized but not tested in manufacturing.
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
The minimum clock period for CSCK is 100 ns. Therefore, the clock generated in Master mode must not
violate this specification.
Assumes 50 pF load on all DCI pins.
CSCK Input Low Time
(CSCK pin is an input)
CSCK Output Low Time
(CSCK pin is an output)
CSCK Input High Time
(CSCK pin is an input)
CSCK Output High Time
(CSCK pin is an output)
CSCK Output Fall Time
(CSCK pin is an output)
CSCK Output Rise Time
(CSCK pin is an output)
CSDO Data Output Fall Time
CSDO Data Output Rise Time
Clock Edge to CSDO Data Valid
Clock Edge to CSDO Tri-Stated
Setup Time of CSDI Data Input
to
CSCK Edge (CSCK pin is input
or output)
Hold Time of CSDI Data Input to
CSCK Edge (CSCK pin is input
or output)
COFS Fall Time
(COFS pin is output)
COFS Rise Time
(COFS pin is output)
Setup Time of COFS Data Input
to CSCK Edge (COFS pin is
input)
Hold Time of COFS Data Input to
CSCK Edge (COFS pin is input)
Characteristic
(1)
(4)
(3)
(4)
(3)
(4)
Preliminary
(4)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature
T
T
CY
CY
2
S MODES) TIMING REQUIREMENTS
Min
/2 + 20
/2 + 20
30
30
10
20
20
20
20
—
—
—
—
—
—
—
Typ
—
—
—
—
10
10
10
10
—
—
—
—
10
10
—
—
(2)
Max
-40°C T
-40°C T
20
—
—
—
—
25
25
25
25
10
—
—
25
25
—
—
2009 Microchip Technology Inc.
Units
A
A
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
+125°C for Extended
+85°C for Industrial
Note 1
Note 1
Conditions
—
—
—
—
—
—
—
—
—
—
—
—
—
—
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