DSPIC33FJ256GP710A-H/PT Microchip Technology, DSPIC33FJ256GP710A-H/PT Datasheet - Page 29
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DSPIC33FJ256GP710A-H/PT
Manufacturer Part Number
DSPIC33FJ256GP710A-H/PT
Description
16 Bit MCU/DSP 100LD 40MIPS 256KB FLASH 100 TQFP 12x12x1mm TRAY
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheet
1.DSPIC33FJ64GP206A-IMR.pdf
(338 pages)
Specifications of DSPIC33FJ256GP710A-H/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
30K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 32x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 140°C
Package / Case
100-TQFP
Processor Series
dsPIC33F
Core
dsPIC
Data Bus Width
16 bit
Interface Type
SPI, I2C, UART, JTAG
Number Of Programmable I/os
35
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 140 C
Mounting Style
SMD/SMT
Development Tools By Supplier
MPLAB IDE Software
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
A/d Bit Size
10 bit
A/d Channels Available
13
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ256GP710A-H/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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3.0
The dsPIC33FJXXXGPX06A/X08A/X10A CPU module
has a 16-bit (data) modified Harvard architecture with an
enhanced instruction set, including significant support for
DSP. The CPU has a 24-bit instruction word with a variable
length opcode field. The Program Counter (PC) is 23 bits
wide and addresses up to 4M x 24 bits of user program
memory space. The actual amount of program memory
implemented varies by device. A single-cycle instruction
prefetch mechanism is used to help maintain throughput
and provides predictable execution. All instructions execute
in a single cycle, with the exception of instructions that
change the program flow, the double word move (MOV.D)
instruction and the table instructions. Overhead-free pro-
gram loop constructs are supported using the DO and
REPEAT instructions, both of which are interruptible at any
point.
The dsPIC33FJXXXGPX06A/X08A/X10A devices have
sixteen, 16-bit working registers in the programmer’s
model. Each of the working registers can serve as a data,
address or address offset register. The 16th working regis-
ter (W15) operates as a software Stack Pointer (SP) for
interrupts and calls.
The dsPIC33FJXXXGPX06A/X08A/X10A instruction set
has two classes of instructions: MCU and DSP. These two
instruction classes are seamlessly integrated into a single
CPU. The instruction set includes many addressing modes
and is designed for optimum C compiler efficiency. For most
instructions, the dsPIC33FJXXXGPX06A/X08A/X10A is
capable of executing a data (or program data) memory
read, a working register (data) read, a data memory write
and a program (instruction) memory read per instruction
cycle. As a result, three parameter instructions can be sup-
ported, allowing A + B = C operations to be executed in a
single cycle.
A block diagram of the CPU is shown in Figure 3-1. The
programmer’s model for the dsPIC33FJXXXGPX06A/
X08A/X10A is shown in Figure 3-2.
3.1
The data space can be addressed as 32K words or
64 Kbytes and is split into two blocks, referred to as X and
Y data memory. Each memory block has its own indepen-
2009 Microchip Technology Inc.
Note 1: This data sheet summarizes the features
2: Some registers and associated bits
CPU
Data Addressing Overview
of
X10A family of devices. However, it is not
intended to be a comprehensive refer-
ence source. To complement the informa-
tion in this data sheet, refer to Section 2.
“CPU” (DS70204) in the “dsPIC33F/
PIC24H
which is available from the Microchip web
site (www.microchip.com).
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
the dsPIC33FJXXXGPX06A/X08A/
Family
dsPIC33FJXXXGPX06A/X08A/X10A
Reference
Manual”,
Preliminary
dent Address Generation Unit (AGU). The MCU class of
instructions operates solely through the X memory AGU,
which accesses the entire memory map as one linear data
space. Certain DSP instructions operate through the X and
Y AGUs to support dual operand reads, which splits the
data address space into two parts. The X and Y data space
boundary is device-specific.
Overhead-free circular buffers (Modulo Addressing mode)
are supported in both X and Y address spaces. The Modulo
Addressing removes the software boundary checking over-
head for DSP algorithms. Furthermore, the X AGU circular
addressing can be used with any of the MCU class of
instructions. The X AGU also supports Bit-Reversed
Addressing to greatly simplify input or output data
reordering for radix-2 FFT algorithms.
The upper 32 Kbytes of the data space memory map can
optionally be mapped into program space at any 16K pro-
gram word boundary defined by the 8-bit Program Space
Visibility Page (PSVPAG) register. The program to data
space mapping feature lets any instruction access program
space as if it were data space. The data space also includes
2 Kbytes of DMA RAM, which is primarily used for DMA
data transfers, but may be used as general purpose RAM.
3.2
The DSP engine features a high-speed, 17-bit by 17-bit
multiplier, a 40-bit ALU, two 40-bit saturating accumula-
tors and a 40-bit bidirectional barrel shifter. The barrel
shifter is capable of shifting a 40-bit value, up to 16 bits
right or left, in a single cycle. The DSP instructions operate
seamlessly with all other instructions and have been
designed for optimal real-time performance. The MAC
instruction and other associated instructions can concur-
rently fetch two data operands from memory while multi-
plying two W registers and accumulating and optionally
saturating the result in the same cycle. This instruction
functionality requires that the RAM memory data space be
split for these instructions and linear for all others. Data
space partitioning is achieved in a transparent and flexible
manner through dedicating certain working registers to
each address space.
3.3
The dsPIC33FJXXXGPX06A/X08A/X10A features a
17-bit by 17-bit, single-cycle multiplier that is shared by
both the MCU ALU and DSP engine. The multiplier can
perform signed, unsigned and mixed-sign multiplication.
Using a 17-bit by 17-bit multiplier for 16-bit by 16-bit mul-
tiplication not only allows you to perform mixed-sign multi-
plication, it also achieves accurate results for special
operations, such as (-1.0) x (-1.0).
The dsPIC33FJXXXGPX06A/X08A/X10A supports 16/16
and 32/16 divide operations, both fractional and integer.
All divide instructions are iterative operations. They must
be executed within a REPEAT loop, resulting in a total exe-
cution time of 19 instruction cycles. The divide operation
can be interrupted during any of those 19 cycles without
loss of data.
A 40-bit barrel shifter is used to perform up to a 16-bit, left
or right shift in a single cycle. The barrel shifter can be used
by both MCU and DSP instructions.
DSP Engine Overview
Special MCU Features
DS70593B-page 29
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