DSPIC33FJ256GP710A-H/PT Microchip Technology, DSPIC33FJ256GP710A-H/PT Datasheet - Page 247
![16 Bit MCU/DSP 100LD 40MIPS 256KB FLASH 100 TQFP 12x12x1mm TRAY](/photos/16/3/160366/tqfp-100_sml.jpg)
DSPIC33FJ256GP710A-H/PT
Manufacturer Part Number
DSPIC33FJ256GP710A-H/PT
Description
16 Bit MCU/DSP 100LD 40MIPS 256KB FLASH 100 TQFP 12x12x1mm TRAY
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheet
1.DSPIC33FJ64GP206A-IMR.pdf
(338 pages)
Specifications of DSPIC33FJ256GP710A-H/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
30K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 32x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 140°C
Package / Case
100-TQFP
Processor Series
dsPIC33F
Core
dsPIC
Data Bus Width
16 bit
Interface Type
SPI, I2C, UART, JTAG
Number Of Programmable I/os
35
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 140 C
Mounting Style
SMD/SMT
Development Tools By Supplier
MPLAB IDE Software
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
A/d Bit Size
10 bit
A/d Channels Available
13
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ256GP710A-H/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- Current page: 247 of 338
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22.0
dsPIC33FJXXXGPX06A/X08A/X10A devices include
the following features intended to maximize application
flexibility and reliability, and minimize cost through elim-
ination of external components:
• Flexible Configuration
• Watchdog Timer (WDT)
• Code Protection and CodeGuard™ Security
• JTAG Boundary Scan Interface
• In-Circuit Serial Programming™ (ICSP™)
• In-Circuit Emulation
TABLE 22-1:
2009 Microchip Technology Inc.
0xF80000 FBS
0xF80002 FSS
0xF80004 FGS
0xF80006 FOSCSEL
0xF80008 FOSC
0xF8000A FWDT
0xF8000C FPOR
0xF8000E FICD
0xF80010 FUID0
0xF80012 FUID1
0xF80014 FUID2
0xF80016 FUID3
Legend: — = unimplemented bit, read as ‘0’.
Address
Note 1: These bits are reserved for use by development tools and must be programmed as ‘1’.
Note 1: This data sheet summarizes the features
2: When read, this bit returns the current programmed value.
3: This bit is unimplemented on dsPIC33FJ64GPX06A/X08A/X10A and dsPIC33FJ128GPX06A/X08A/X10A
4: These bits are reserved and always read as ‘1’.
2: Some registers and associated bits
SPECIAL FEATURES
devices and reads as ‘0’.
of
X10A family of devices. However, it is not
intended to be a comprehensive refer-
ence source. To complement the informa-
tion in this data sheet, refer to Section
23.
(DS70199), Section 24. “Programming
and Diagnostics” (DS70207), and Sec-
tion
(DS70194) in the “dsPIC33F/PIC24H
Family Reference Manual”, which are
available from the Microchip web site
(www.microchip.com).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Name
the dsPIC33FJXXXGPX06A/X08A/
DEVICE CONFIGURATION REGISTER MAP
25.
“CodeGuard™
FWDTEN
dsPIC33FJXXXGPX06A/X08A/X10A
“Device
IESO
Bit 7
—
FCKSM<1:0>
Reserved
RBS<1:0>
RSS<1:0>
Reserved
Reserved
Configuration”
WINDIS
Bit 6
(1)
—
Security”
(2)
(4)
PLLKEN
Preliminary
JTAGEN
Bit 5
—
—
—
—
—
(3)
User Unit ID Byte 0
User Unit ID Byte 1
User Unit ID Byte 2
User Unit ID Byte 3
WDTPRE
22.1
The Configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’), to select
various device configurations. These bits are mapped
starting at program memory location 0xF80000.
The device Configuration register map is shown in
Table 22-1.
The individual Configuration bit descriptions for the
Configuration registers are shown in Table 22-2.
Note that address 0xF80000 is beyond the user program
memory space. In fact, it belongs to the configuration
memory space (0x800000-0xFFFFFF) which can only be
accessed using table reads and table writes.
To prevent inadvertent configuration changes during
code execution, all programmable Configuration bits
are write-once. After a bit is initially programmed during
a power cycle, it cannot be written to again. Changing
a device configuration requires that power to the device
be cycled.
Bit 4
—
—
—
—
—
—
—
Configuration Bits
Bit 3
—
—
—
—
—
BSS<2:0>
SSS<2:0>
OSCIOFNC POSCMD<1:0>
WDTPOST<3:0>
GSS1
Bit 2
—
FPWRT<2:0>
FNOSC<2:0>
DS70593B-page 247
GSS0
Bit 1
ICS<1:0>
GWRP
BWRP
SWRP
Bit 0
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