EP2SGX90EF1152C3 Altera, EP2SGX90EF1152C3 Datasheet - Page 121

• Manufacturer Part Number: EP2SGX90EF1152C3
• Description: Stratix II GX
• Manufacturer: Altera

Figure 2–77. Row I/O Block Connection to the Interconnect
Note to
(1)
Altera Corporation
October 2007
Interconnect
The 32 data and control signals consist of eight data out lines: four lines each for DDR applications
io_dataouta[3..0] and io_dataoutb[3..0], four output enables io_oe[3..0], four input clock enables
io_ce_in[3..0], four output clock enables io_ce_out[3..0], four clocks io_clk[3..0], four asynchronous
clear and preset signals io_aclr/apreset[3..0], and four synchronous clear and preset signals
io_sclr/spreset[3..0].
LAB Local
Figure
Interconnects
to Adjacent LAB
R4 & R24
Interconnect
2–77:
Direct Link
LAB
Figure 2–77
io_dataina[3..0]
io_datainb[3..0]
C4 Interconnect
to Adjacent LAB
shows how a row I/O block connects to the logic array.
Interconnect
Direct Link
I/O Block Local
Interconnect
io_clk[7:0]
Stratix II GX Device Handbook, Volume 1
32
Horizontal
I/O Block
up to Four IOEs
Block Contains
Horizontal I/O
Stratix II GX Architecture
32 Data & Control
Signals from
Logic Array (1)
2–113