EP2SGX90EF1152C3 Altera, EP2SGX90EF1152C3 Datasheet - Page 149

• Manufacturer Part Number: EP2SGX90EF1152C3
• Description: Stratix II GX
• Manufacturer: Altera

Figure 2–90. Fast PLL and Channel Layout in the EP2SGX30C/D and EP2SGX60C/D Devices
Note to
(1)
Altera Corporation
October 2007
See
Figure
Table 2–38
2–90:
4
for the number of channels each device supports.
2
2
4
4
For high-speed source synchronous interfaces such as POS-PHY 4 and the
Parallel RapidIO standard, the source synchronous clock rate is not a
byte- or SERDES-rate multiple of the data rate. Byte alignment is
necessary for these protocols because the source synchronous clock does
not provide a byte or word boundary since the clock is one half the data
rate, not one eighth. The Stratix II GX device’s high-speed differential I/O
circuitry provides dedicated data realignment circuitry for
user-controlled byte boundary shifting. This simplifies designs while
saving ALM resources. You can use an ALM-based state machine to
signal the shift of receiver byte boundaries until a specified pattern is
detected to indicate byte alignment.
Fast PLL and Channel Layout
The receiver and transmitter channels are interleaved such that each I/O
bank on the left side of the device has one receiver channel and one
transmitter channel per LAB row.
channel layout in the EP2SGX30C/D and EP2SGX60C/D devices.
Figure 2–91
EP2SGX90E/F, and EP2SGX130G devices.
PLL 1
PLL 2
Fast
Fast
LVDS
LVDS
Clock
Clock
shows the fast PLL and channel layout in EP2SGX60E,
Clock
Clock
DPA
DPA
Quadrant
Quadrant
Stratix II GX Device Handbook, Volume 1
Figure 2–90
shows the fast PLL and
Quadrant
Quadrant
Stratix II GX Architecture
Note (1)
2–141