EP2SGX90EF1152C3 Altera, EP2SGX90EF1152C3 Datasheet - Page 271
EP2SGX90EF1152C3
Manufacturer Part Number
EP2SGX90EF1152C3
Description
Stratix II GX
Manufacturer
Altera
Datasheet
1.EP2SGX90EF1152C3.pdf
(316 pages)
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(1)
Class II
Differential SSTL-18
Class I
Class I I
1.8-V differential
HSTL Class I
1.8-V differential
HSTL Class I I
HSTL Class I
HSTL Class II
Differential SSTL-18
1.8-V HSTL CLass I
Differential SSTL-2
1.5-V differential
1.5-V differential
LVDS
HyperTransport
LVTTL
2.5 V
1.8 V
1.5 V
LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
Table 4–89. Stratix II GX Maximum Input Clock Rate for Row I/O Pins (Part 2 of 2)
Table 4–90. Stratix II GX Maximum Input Clock Rate for Dedicated Clock Pins (Part 1 of 2)
I/O Standard
I/O Standard
The parameters are only available on the left side of the device.
(1)
-3 Speed Grade
-3 Speed Grade
Table 4–90
device dedicated clock pins.
500
500
500
500
500
500
500
520
520
500
500
500
500
500
500
500
500
500
500
500
500
shows the maximum input clock toggle rates for Stratix II GX
-4 Speed Grade
-4 Speed Grade
500
500
500
500
500
500
500
520
520
500
500
500
500
500
500
500
500
500
500
500
500
-5 Speed Grade
-5 Speed Grade
500
500
500
500
500
500
500
420
420
400
400
400
400
400
500
500
500
500
500
500
500
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
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