EP2SGX90EF1152C3 Altera, EP2SGX90EF1152C3 Datasheet - Page 43

• Manufacturer Part Number: EP2SGX90EF1152C3
• Description: Stratix II GX
• Manufacturer: Altera

Altera Corporation
October 2007
Transceiver Clocking
Each Stratix II GX device transceiver block contains two transmitter PLLs
and four receiver PLLs. These PLLs can be driven by either of the two
reference clocks per transceiver block. These REFCLK signals can drive all
global clocks, transmitter PLL inputs, and all receiver PLL inputs.
Subsequently, the transmitter PLL output can only drive global clock
lines and the receiver PLL reference clock port. Only one of the two
reference clocks in a quad can drive the Inter Quad (I/Q) lines to clock the
PLLs in the other quads.
Figure 2–29
global clock connections for the EP2SGX130 device.
shows the inter-transceiver line connections as well as the
Stratix II GX Device Handbook, Volume 1
Stratix II GX Architecture
2–35